ADC_3Channal/ADC.prj
ADC_3Channal/ADC.prj.convert.9.0.bak
ADC_3Channal/assert.log
ADC_3Channal/designer/impl1/ADC.adb
ADC_3Channal/designer/impl1/ADC.dtf/verify.log
ADC_3Channal/designer/impl1/ADC.ide_des
ADC_3Channal/designer/impl1/ADC.pdb
ADC_3Channal/designer/impl1/ADC.pdb.depends
ADC_3Channal/designer/impl1/ADC.stp
ADC_3Channal/designer/impl1/ADC.tcl
ADC_3Channal/designer/impl1/ADC_1_fp/$$FlashPro_75298.L$$
ADC_3Channal/designer/impl1/ADC_1_fp/ADC.log
ADC_3Channal/designer/impl1/ADC_1_fp/projectData/ADC.pdb
ADC_3Channal/designer/impl1/ADC_1_fp/ADC.pro
ADC_3Channal/designer/impl1/ADC_fp/$$FlashPro_75298.L$$
ADC_3Channal/designer/impl1/ADC_fp/ADC.log
ADC_3Channal/designer/impl1/ADC_fp/projectData/ADC.pdb
ADC_3Channal/designer/impl1/ADC_fp/projectData/ADC_test.pdb
ADC_3Channal/designer/impl1/ADC_fp/ADC.pro
ADC_3Channal/designer/impl1/designer.log
ADC_3Channal/designer/impl1/designer_genhdl.log
ADC_3Channal/designer/impl1/designer_synth_check.log
ADC_3Channal/designer/impl1/MY_ADC.ide_des
ADC_3Channal/designer/impl1/MY_ADC.tcl
ADC_3Channal/designer/impl1/pllclk.ide_des
ADC_3Channal/hdl/ADC.v
ADC_3Channal/simulation/modelsim.ini.sav
ADC_3Channal/simulation/modelsim.ini
ADC_3Channal/simulation/MY_ADC_acm_ram_R0C0.mem
ADC_3Channal/smartgen/MY_ADC/MY_ADC.cfg
ADC_3Channal/smartgen/MY_ADC/MY_ADC.gen
ADC_3Channal/smartgen/MY_ADC/MY_ADC.log
ADC_3Channal/smartgen/MY_ADC/MY_ADC.ncf
ADC_3Channal/smartgen/MY_ADC/MY_ADC.v
ADC_3Channal/smartgen/MY_ADC/MY_ADC_abdelay_counter.v
ADC_3Channal/smartgen/MY_ADC/MY_ADC_acm.mem
ADC_3Channal/smartgen/MY_ADC/MY_ADC_acm_ram.hex
ADC_3Channal/smartgen/MY_ADC/MY_ADC_acm_ram_R0C0.mem
ADC_3Channal/smartgen/MY_ADC/MY_ADC.cxf
ADC_3Channal/smartgen/pllclk/pllclk.gen
ADC_3Channal/smartgen/pllclk/pllclk.log
ADC_3Channal/smartgen/pllclk/pllclk.v
ADC_3Channal/smartgen/pllclk/pllclk.cxf
ADC_3Channal/smartgen/smartgen.aws
ADC_3Channal/smartgen/MY_ADC_work.ixf
ADC_3Channal/smartgen/pllclk_work.ixf
ADC_3Channal/synthesis/ADC.areasrr
ADC_3Channal/synthesis/ADC.edn
ADC_3Channal/synthesis/ADC.fse
ADC_3Channal/synthesis/ADC.htm
ADC_3Channal/synthesis/ADC.map
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ADC_3Channal/synthesis/ADC.sap
ADC_3Channal/synthesis/ADC.sdf
ADC_3Channal/synthesis/ADC.so
ADC_3Channal/synthesis/ADC.srd
ADC_3Channal/synthesis/ADC.srl
ADC_3Channal/synthesis/ADC.srm
ADC_3Channal/synthesis/ADC.szr
ADC_3Channal/synthesis/ADC.tlg
ADC_3Channal/synthesis/ADC_drc.rpt
ADC_3Channal/synthesis/ADC_sdc.sdc
ADC_3Channal/synthesis/backup/ADC.srr
ADC_3Channal/synthesis/backup/MY_ADC.srr
ADC_3Channal/synthesis/dm/ADC.xdm
ADC_3Channal/synthesis/dm/MY_ADC.xdm
ADC_3Channal/synthesis/MY_ADC.areasrr
ADC_3Channal/synthesis/MY_ADC.edn
ADC_3Channal/synthesis/MY_ADC.fse
ADC_3Channal/synthesis/MY_ADC.htm
ADC_3Channal/synthesis/MY_ADC.map
ADC_3Channal/synthesis/MY_ADC.pdc
ADC_3Channal/synthesis/MY_ADC.sap
ADC_3Channal/synthesis/MY_ADC.sdf
ADC_3Channal/synthesis/MY_ADC.so
ADC_3Channal/synthesis/MY_ADC.srd
ADC_3Channal/synthesis/MY_ADC.srl
ADC_3Channal/synthesis/MY_ADC.srm
ADC_3Channal/synthesis/MY_ADC.srr
ADC_3Channal/synthesis/MY_ADC.srs
ADC_3Channal/synthesis/MY_ADC.szr
ADC_3Channal/synthesis/MY_ADC.tlg
ADC_3Channal/synthesis/MY_ADC_drc.rpt
ADC_3Channal/synthesis/MY_ADC_sdc.sdc
ADC_3Channal/synthesis/run_options.txt
ADC_3Channal/synthesis/scratchproject.prs
ADC_3Channal/synthesis/stdout.log
ADC_3Channal/synthesis/synlog/ADC_Fusion_Mapper.srr
ADC_3Channal/synthesis/synlog/ADC_Fusion_Mapper.srr_Min
ADC_3Channal/synthesis/synlog/ADC_Fusion_Mapper.szr
ADC_3Channal/synthesis/synlog/MY_ADC_Fusion_Mapper.srr
ADC_3Channal/synthesis/synlog/MY_ADC_Fusion_Mapper.srr_Min
ADC_3Channal/synthesis/synlog/MY_ADC_Fusion_Mapper.szr
ADC_3Channal/synthesis/syntmp/ADC.msg
ADC_3Channal/synthesis/syntmp/ADC.plg
ADC_3Channal/synthesis/syntmp/ADC_flink.htm
ADC_3Channal/synthesis/syntmp/ADC_srr.htm
ADC_3Channal/synthesis/syntmp/ADC_toc.htm
ADC_3Channal/synthesis/syntmp/closed.png
ADC_3Channal/synthesis/syntmp/cmdrec_compiler.log
ADC_3Channal/synthesis/syntmp/cmdrec_fusion_mapper.log
ADC_3Channal/synthesis/syntmp/MY_ADC.msg
ADC_3Channal/synthesis/syntmp/MY_ADC.plg
ADC_3Channal/synthesis/syntmp/MY_ADC_flink.htm
ADC_3Channal/synthesis/syntmp/MY_ADC_srr.htm
ADC_3Channal/synthesis/syntmp/MY_ADC_toc.htm
ADC_3Channal/synthesis/syntmp/open.png
ADC_3Channal/synthesis/syntmp/sap.log
ADC_3Channal/synthesis/MY_ADC_syn.prj
ADC_3Channal/synthesis/ADC_syn.prj
ADC_3Channal/synthesis/ADC.srr
ADC_3Channal/synthesis/identify.log
ADC_3Channal/synthesis/ADC.srs
ADC_3Channal/viewdraw/vf/project.lst
ADC_3Channal/viewdraw/viewdraw.ini
ADC_3Channal/designer/impl1/ADC_1_fp/projectData
ADC_3Channal/designer/impl1/ADC_fp/projectData
ADC_3Channal/designer/impl1/ADC.dtf
ADC_3Channal/designer/impl1/ADC_1_fp
ADC_3Channal/designer/impl1/ADC_fp
ADC_3Channal/designer/impl1/simulation
ADC_3Channal/designer/impl1
ADC_3Channal/smartgen/MY_ADC
ADC_3Channal/smartgen/pllclk
ADC_3Channal/smartgen/common
ADC_3Channal/synthesis/backup
ADC_3Channal/synthesis/dm
ADC_3Channal/synthesis/synlog
ADC_3Channal/synthesis/syntmp
ADC_3Channal/synthesis/coreip
ADC_3Channal/viewdraw/vf
ADC_3Channal/viewdraw/sch
ADC_3Channa