文件名称:SIMULATION-AND-SYNTHESIS-OF-TRIPLE-DES-BLOCK-CIPH
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- 上传时间：2013-04-02
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文件大小：5.12mb
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This project presents FPGA implementations of the DES and Triple-DES with improved security against power analysis attacks. The proposed designs use Boolean masking, a previously introduced technique to protect smart card implementations from these attacks. Triple DES was the answer to many of the shortcomings of DES. Since it is based on the DES algorithm, it is very easy to modify existing software to use Triple DES. It also has the advantage of proven reliability and a longer key length that eliminates many of the shortcut attacks that can be used to reduce the amount of time it takes to break DES. However, even this more powerful version of DES may not be strong enough to protect data for very much longer. The DES algorithm itself has become obsolete and is in need of replacement.DES encrypts data in 64-bit and it is a symmetric algorithm. The key length is 56-bits.
KEY WORDS: DES, Encryption, Decryption, Cryptography, Simulation, Synthesis, TDES, Cipher.
KEY WORDS: DES, Encryption, Decryption, Cryptography, Simulation, Synthesis, TDES, Cipher.
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SIMULATION AND SYNTHESIS OF TRIPLE-DES BLOCK CIPHER USING VHDL/PROJECT/
SIMULATION AND SYNTHESIS OF TRIPLE-DES BLOCK CIPHER USING VHDL/PROJECT/2003.ppt
SIMULATION AND SYNTHESIS OF TRIPLE-DES BLOCK CIPHER USING VHDL/PROJECT/add_key.bmp
SIMULATION AND SYNTHESIS OF TRIPLE-DES BLOCK CIPHER USING VHDL/PROJECT/add_left.bmp
SIMULATION AND SYNTHESIS OF TRIPLE-DES BLOCK CIPHER USING VHDL/PROJECT/blocktopofdes.bmp
SIMULATION AND SYNTHESIS OF TRIPLE-DES BLOCK CIPHER USING VHDL/PROJECT/CHAPTER.doc
SIMULATION AND SYNTHESIS OF TRIPLE-DES BLOCK CIPHER USING VHDL/PROJECT/expansiontable.bmp
SIMULATION AND SYNTHESIS OF TRIPLE-DES BLOCK CIPHER USING VHDL/PROJECT/pbox_tb.bmp
SIMULATION AND SYNTHESIS OF TRIPLE-DES BLOCK CIPHER USING VHDL/PROJECT/s1_box.bmp
SIMULATION AND SYNTHESIS OF TRIPLE-DES BLOCK CIPHER USING VHDL/PROJECT/sbox.bmp
SIMULATION AND SYNTHESIS OF TRIPLE-DES BLOCK CIPHER USING VHDL/PROJECT/SOURCE CODE.doc
SIMULATION AND SYNTHESIS OF TRIPLE-DES BLOCK CIPHER USING VHDL/PROJECT/TECHINICAL PAPER REPORT.doc
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SIMULATION AND SYNTHESIS OF TRIPLE-DES BLOCK CIPHER USING VHDL/PROJECT/2003.ppt
SIMULATION AND SYNTHESIS OF TRIPLE-DES BLOCK CIPHER USING VHDL/PROJECT/add_key.bmp
SIMULATION AND SYNTHESIS OF TRIPLE-DES BLOCK CIPHER USING VHDL/PROJECT/add_left.bmp
SIMULATION AND SYNTHESIS OF TRIPLE-DES BLOCK CIPHER USING VHDL/PROJECT/blocktopofdes.bmp
SIMULATION AND SYNTHESIS OF TRIPLE-DES BLOCK CIPHER USING VHDL/PROJECT/CHAPTER.doc
SIMULATION AND SYNTHESIS OF TRIPLE-DES BLOCK CIPHER USING VHDL/PROJECT/expansiontable.bmp
SIMULATION AND SYNTHESIS OF TRIPLE-DES BLOCK CIPHER USING VHDL/PROJECT/pbox_tb.bmp
SIMULATION AND SYNTHESIS OF TRIPLE-DES BLOCK CIPHER USING VHDL/PROJECT/s1_box.bmp
SIMULATION AND SYNTHESIS OF TRIPLE-DES BLOCK CIPHER USING VHDL/PROJECT/sbox.bmp
SIMULATION AND SYNTHESIS OF TRIPLE-DES BLOCK CIPHER USING VHDL/PROJECT/SOURCE CODE.doc
SIMULATION AND SYNTHESIS OF TRIPLE-DES BLOCK CIPHER USING VHDL/PROJECT/TECHINICAL PAPER REPORT.doc
Photo0035.jpg
Photo0032.jpg
Photo0034.jpg
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