文件名称:mydesign.rar
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基于FPGA的直接序列扩频发射机的设计与仿真。实验中以QuartusII 7.2 为设计和仿真工具，
各模块采用Verilog HDL设计并封装，顶层使用图形设计方式,最后得到的仿真结果使用Matlab描点来绘制出波形。
,FPGA-based direct sequence spread spectrum transmitter of the design and simulation. Experiment to QuartusII 7.2 for the design and simulation tools, the module using Verilog HDL to design and package, the top-level use of graphic design, and finally the simulation results obtained using the Matlab descr iption points to draw waveforms.
各模块采用Verilog HDL设计并封装，顶层使用图形设计方式,最后得到的仿真结果使用Matlab描点来绘制出波形。
,FPGA-based direct sequence spread spectrum transmitter of the design and simulation. Experiment to QuartusII 7.2 for the design and simulation tools, the module using Verilog HDL to design and package, the top-level use of graphic design, and finally the simulation results obtained using the Matlab descr iption points to draw waveforms.
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下载文件列表
mydesign/add1.v
mydesign/add2.v
mydesign/addr_ctrl.bsf
mydesign/addr_ctrl.v
mydesign/addr_ctrl.v.bak
mydesign/addr_ctrl.vwf
mydesign/clock.asm.rpt
mydesign/clock.bsf
mydesign/clock.done
mydesign/clock.fit.rpt
mydesign/clock.fit.smsg
mydesign/clock.fit.summary
mydesign/clock.flow.rpt
mydesign/clock.map.rpt
mydesign/clock.map.smsg
mydesign/clock.map.summary
mydesign/clock.pin
mydesign/clock.qpf
mydesign/clock.qsf
mydesign/clock.qws
mydesign/clock.sim.rpt
mydesign/clock.tan.rpt
mydesign/clock.tan.summary
mydesign/clock.v
mydesign/clock.v.bak
mydesign/clock.vwf
mydesign/convolute.bsf
mydesign/convolute.v
mydesign/convolute.v.bak
mydesign/convolute.vwf
mydesign/db/add_sub_0sh.tdf
mydesign/db/add_sub_1sh.tdf
mydesign/db/add_sub_fah.tdf
mydesign/db/add_sub_fnh.tdf
mydesign/db/add_sub_gah.tdf
mydesign/db/add_sub_ndh.tdf
mydesign/db/add_sub_nqh.tdf
mydesign/db/add_sub_odh.tdf
mydesign/db/add_sub_ooh.tdf
mydesign/db/add_sub_poh.tdf
mydesign/db/altsyncram_d591.tdf
mydesign/db/altsyncram_vc91.tdf
mydesign/db/clock.(0).cnf.cdb
mydesign/db/clock.(0).cnf.hdb
mydesign/db/clock.(1).cnf.cdb
mydesign/db/clock.(1).cnf.hdb
mydesign/db/clock.(10).cnf.cdb
mydesign/db/clock.(10).cnf.hdb
mydesign/db/clock.(11).cnf.cdb
mydesign/db/clock.(11).cnf.hdb
mydesign/db/clock.(12).cnf.cdb
mydesign/db/clock.(12).cnf.hdb
mydesign/db/clock.(13).cnf.cdb
mydesign/db/clock.(13).cnf.hdb
mydesign/db/clock.(14).cnf.cdb
mydesign/db/clock.(14).cnf.hdb
mydesign/db/clock.(15).cnf.cdb
mydesign/db/clock.(15).cnf.hdb
mydesign/db/clock.(16).cnf.cdb
mydesign/db/clock.(16).cnf.hdb
mydesign/db/clock.(17).cnf.cdb
mydesign/db/clock.(17).cnf.hdb
mydesign/db/clock.(18).cnf.cdb
mydesign/db/clock.(18).cnf.hdb
mydesign/db/clock.(19).cnf.cdb
mydesign/db/clock.(19).cnf.hdb
mydesign/db/clock.(2).cnf.cdb
mydesign/db/clock.(2).cnf.hdb
mydesign/db/clock.(20).cnf.cdb
mydesign/db/clock.(20).cnf.hdb
mydesign/db/clock.(21).cnf.cdb
mydesign/db/clock.(21).cnf.hdb
mydesign/db/clock.(22).cnf.cdb
mydesign/db/clock.(22).cnf.hdb
mydesign/db/clock.(23).cnf.cdb
mydesign/db/clock.(23).cnf.hdb
mydesign/db/clock.(24).cnf.cdb
mydesign/db/clock.(24).cnf.hdb
mydesign/db/clock.(25).cnf.cdb
mydesign/db/clock.(25).cnf.hdb
mydesign/db/clock.(26).cnf.cdb
mydesign/db/clock.(26).cnf.hdb
mydesign/db/clock.(27).cnf.cdb
mydesign/db/clock.(27).cnf.hdb
mydesign/db/clock.(28).cnf.cdb
mydesign/db/clock.(28).cnf.hdb
mydesign/db/clock.(3).cnf.cdb
mydesign/db/clock.(3).cnf.hdb
mydesign/db/clock.(4).cnf.cdb
mydesign/db/clock.(4).cnf.hdb
mydesign/db/clock.(5).cnf.cdb
mydesign/db/clock.(5).cnf.hdb
mydesign/db/clock.(6).cnf.cdb
mydesign/db/clock.(6).cnf.hdb
mydesign/db/clock.(7).cnf.cdb
mydesign/db/clock.(7).cnf.hdb
mydesign/db/clock.(8).cnf.cdb
mydesign/db/clock.(8).cnf.hdb
mydesign/db/clock.(9).cnf.cdb
mydesign/db/clock.(9).cnf.hdb
mydesign/db/clock.asm.qmsg
mydesign/db/clock.cbx.xml
mydesign/db/clock.cmp.cdb
mydesign/db/clock.cmp.hdb
mydesign/db/clock.cmp.logdb
mydesign/db/clock.cmp.rdb
mydesign/db/clock.cmp.tdb
mydesign/db/clock.cmp0.ddb
mydesign/db/clock.cmp2.ddb
mydesign/db/clock.dbp
mydesign/db/clock.db_info
mydesign/db/clock.eco.cdb
mydesign/db/clock.eds_overflow
mydesign/db/clock.fit.qmsg
mydesign/db/clock.hier_info
mydesign/db/clock.hif
mydesign/db/clock.map.cdb
mydesign/db/clock.map.hdb
mydesign/db/clock.map.logdb
mydesign/db/clock.map.qmsg
mydesign/db/clock.pre_map.cdb
mydesign/db/clock.pre_map.hdb
mydesign/db/clock.psp
mydesign/db/clock.pss
mydesign/db/clock.rpp.qmsg
mydesign/db/clock.rtlv.hdb
mydesign/db/clock.rtlv_sg.cdb
mydesign/db/clock.rtlv_sg_swap.cdb
mydesign/db/clock.sgate.rvd
mydesign/db/clock.sgate_sm.rvd
mydesign/db/clock.sgdiff.cdb
mydesign/db/clock.sgdiff.hdb
mydesign/db/clock.sim.cvwf
mydesign/db/clock.sim.hdb
mydesign/db/clock.sim.qmsg
mydesign/db/clock.sim.rdb
mydesign/db/clock.sld_design_entry.sci
mydesign/db/clock.sld_design_entry_dsc.sci
mydesign/db/clock.syn_hier_info
mydesign/db/clock.tan.qmsg
mydesign/db/clock.tis_db_list.ddb
mydesign/db/mult_dns.tdf
mydesign/db/prev_cmp_clock.asm.qmsg
mydesign/db/prev_cmp_clock.fit.qmsg
mydesign/db/prev_cmp_clock.map.qmsg
mydesign/db/prev_cmp_clock.qmsg
mydesign/db/prev_cmp_clock.sim.qmsg
mydesign/db/prev_cmp_clock.tan.qmsg
mydesign/db/wed.wsf
mydesign/db
mydesign/dsss.bsf
mydesign/dsss.v
mydesign/dsss.v.bak
mydesign/dsss.vwf
mydesign/fir.bsf
mydesign/fir.v
mydesign/insert.bsf
mydesign/insert.v
mydesign/insert.v.bak
mydesign/insert.vwf
mydesign/jilian.bdf
mydesign/jilian.bsf
mydesign/jilian.v
mydesign/jilian.vwf
mydesign/jl.bsf
mydesign/juanji1.v
mydesign/juanji1.v.bak
mydesign/juanji1.vwf
mydesign/j_l.bsf
mydesign/kasami.bsf
mydesign/kasami.v
mydesign/kasami.v.bak
mydesign/kasami.vwf
mydesign/laoshu.v
mydesign/laoshu.v.bak
mydesign/laoshu.vwf
mydesign/lw.mif
mydesign/mult1.v
mydesign/mult2.v
mydesign/mult3.v
mydesign/mult4.v
mydesign/mult5.v
mydesign/mult6.v
mydesign/mult7.v
mydesign/mult8.v
mydesign/rom.bsf
mydesign/rom.v
mydesign/rom_bb.v
mydesign/ss.bdf
mydesign/ss.v.bak
mydesign/ss.vwf
mydesign/test.bdf
mydesign/test.vwf
mydesign/two.bdf
mydesign/two.vwf
mydesign
mydesign/add2.v
mydesign/addr_ctrl.bsf
mydesign/addr_ctrl.v
mydesign/addr_ctrl.v.bak
mydesign/addr_ctrl.vwf
mydesign/clock.asm.rpt
mydesign/clock.bsf
mydesign/clock.done
mydesign/clock.fit.rpt
mydesign/clock.fit.smsg
mydesign/clock.fit.summary
mydesign/clock.flow.rpt
mydesign/clock.map.rpt
mydesign/clock.map.smsg
mydesign/clock.map.summary
mydesign/clock.pin
mydesign/clock.qpf
mydesign/clock.qsf
mydesign/clock.qws
mydesign/clock.sim.rpt
mydesign/clock.tan.rpt
mydesign/clock.tan.summary
mydesign/clock.v
mydesign/clock.v.bak
mydesign/clock.vwf
mydesign/convolute.bsf
mydesign/convolute.v
mydesign/convolute.v.bak
mydesign/convolute.vwf
mydesign/db/add_sub_0sh.tdf
mydesign/db/add_sub_1sh.tdf
mydesign/db/add_sub_fah.tdf
mydesign/db/add_sub_fnh.tdf
mydesign/db/add_sub_gah.tdf
mydesign/db/add_sub_ndh.tdf
mydesign/db/add_sub_nqh.tdf
mydesign/db/add_sub_odh.tdf
mydesign/db/add_sub_ooh.tdf
mydesign/db/add_sub_poh.tdf
mydesign/db/altsyncram_d591.tdf
mydesign/db/altsyncram_vc91.tdf
mydesign/db/clock.(0).cnf.cdb
mydesign/db/clock.(0).cnf.hdb
mydesign/db/clock.(1).cnf.cdb
mydesign/db/clock.(1).cnf.hdb
mydesign/db/clock.(10).cnf.cdb
mydesign/db/clock.(10).cnf.hdb
mydesign/db/clock.(11).cnf.cdb
mydesign/db/clock.(11).cnf.hdb
mydesign/db/clock.(12).cnf.cdb
mydesign/db/clock.(12).cnf.hdb
mydesign/db/clock.(13).cnf.cdb
mydesign/db/clock.(13).cnf.hdb
mydesign/db/clock.(14).cnf.cdb
mydesign/db/clock.(14).cnf.hdb
mydesign/db/clock.(15).cnf.cdb
mydesign/db/clock.(15).cnf.hdb
mydesign/db/clock.(16).cnf.cdb
mydesign/db/clock.(16).cnf.hdb
mydesign/db/clock.(17).cnf.cdb
mydesign/db/clock.(17).cnf.hdb
mydesign/db/clock.(18).cnf.cdb
mydesign/db/clock.(18).cnf.hdb
mydesign/db/clock.(19).cnf.cdb
mydesign/db/clock.(19).cnf.hdb
mydesign/db/clock.(2).cnf.cdb
mydesign/db/clock.(2).cnf.hdb
mydesign/db/clock.(20).cnf.cdb
mydesign/db/clock.(20).cnf.hdb
mydesign/db/clock.(21).cnf.cdb
mydesign/db/clock.(21).cnf.hdb
mydesign/db/clock.(22).cnf.cdb
mydesign/db/clock.(22).cnf.hdb
mydesign/db/clock.(23).cnf.cdb
mydesign/db/clock.(23).cnf.hdb
mydesign/db/clock.(24).cnf.cdb
mydesign/db/clock.(24).cnf.hdb
mydesign/db/clock.(25).cnf.cdb
mydesign/db/clock.(25).cnf.hdb
mydesign/db/clock.(26).cnf.cdb
mydesign/db/clock.(26).cnf.hdb
mydesign/db/clock.(27).cnf.cdb
mydesign/db/clock.(27).cnf.hdb
mydesign/db/clock.(28).cnf.cdb
mydesign/db/clock.(28).cnf.hdb
mydesign/db/clock.(3).cnf.cdb
mydesign/db/clock.(3).cnf.hdb
mydesign/db/clock.(4).cnf.cdb
mydesign/db/clock.(4).cnf.hdb
mydesign/db/clock.(5).cnf.cdb
mydesign/db/clock.(5).cnf.hdb
mydesign/db/clock.(6).cnf.cdb
mydesign/db/clock.(6).cnf.hdb
mydesign/db/clock.(7).cnf.cdb
mydesign/db/clock.(7).cnf.hdb
mydesign/db/clock.(8).cnf.cdb
mydesign/db/clock.(8).cnf.hdb
mydesign/db/clock.(9).cnf.cdb
mydesign/db/clock.(9).cnf.hdb
mydesign/db/clock.asm.qmsg
mydesign/db/clock.cbx.xml
mydesign/db/clock.cmp.cdb
mydesign/db/clock.cmp.hdb
mydesign/db/clock.cmp.logdb
mydesign/db/clock.cmp.rdb
mydesign/db/clock.cmp.tdb
mydesign/db/clock.cmp0.ddb
mydesign/db/clock.cmp2.ddb
mydesign/db/clock.dbp
mydesign/db/clock.db_info
mydesign/db/clock.eco.cdb
mydesign/db/clock.eds_overflow
mydesign/db/clock.fit.qmsg
mydesign/db/clock.hier_info
mydesign/db/clock.hif
mydesign/db/clock.map.cdb
mydesign/db/clock.map.hdb
mydesign/db/clock.map.logdb
mydesign/db/clock.map.qmsg
mydesign/db/clock.pre_map.cdb
mydesign/db/clock.pre_map.hdb
mydesign/db/clock.psp
mydesign/db/clock.pss
mydesign/db/clock.rpp.qmsg
mydesign/db/clock.rtlv.hdb
mydesign/db/clock.rtlv_sg.cdb
mydesign/db/clock.rtlv_sg_swap.cdb
mydesign/db/clock.sgate.rvd
mydesign/db/clock.sgate_sm.rvd
mydesign/db/clock.sgdiff.cdb
mydesign/db/clock.sgdiff.hdb
mydesign/db/clock.sim.cvwf
mydesign/db/clock.sim.hdb
mydesign/db/clock.sim.qmsg
mydesign/db/clock.sim.rdb
mydesign/db/clock.sld_design_entry.sci
mydesign/db/clock.sld_design_entry_dsc.sci
mydesign/db/clock.syn_hier_info
mydesign/db/clock.tan.qmsg
mydesign/db/clock.tis_db_list.ddb
mydesign/db/mult_dns.tdf
mydesign/db/prev_cmp_clock.asm.qmsg
mydesign/db/prev_cmp_clock.fit.qmsg
mydesign/db/prev_cmp_clock.map.qmsg
mydesign/db/prev_cmp_clock.qmsg
mydesign/db/prev_cmp_clock.sim.qmsg
mydesign/db/prev_cmp_clock.tan.qmsg
mydesign/db/wed.wsf
mydesign/db
mydesign/dsss.bsf
mydesign/dsss.v
mydesign/dsss.v.bak
mydesign/dsss.vwf
mydesign/fir.bsf
mydesign/fir.v
mydesign/insert.bsf
mydesign/insert.v
mydesign/insert.v.bak
mydesign/insert.vwf
mydesign/jilian.bdf
mydesign/jilian.bsf
mydesign/jilian.v
mydesign/jilian.vwf
mydesign/jl.bsf
mydesign/juanji1.v
mydesign/juanji1.v.bak
mydesign/juanji1.vwf
mydesign/j_l.bsf
mydesign/kasami.bsf
mydesign/kasami.v
mydesign/kasami.v.bak
mydesign/kasami.vwf
mydesign/laoshu.v
mydesign/laoshu.v.bak
mydesign/laoshu.vwf
mydesign/lw.mif
mydesign/mult1.v
mydesign/mult2.v
mydesign/mult3.v
mydesign/mult4.v
mydesign/mult5.v
mydesign/mult6.v
mydesign/mult7.v
mydesign/mult8.v
mydesign/rom.bsf
mydesign/rom.v
mydesign/rom_bb.v
mydesign/ss.bdf
mydesign/ss.v.bak
mydesign/ss.vwf
mydesign/test.bdf
mydesign/test.vwf
mydesign/two.bdf
mydesign/two.vwf
mydesign
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