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文件名称:dual_RAM.rar

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-09-04
  • 文件大小：
    593.89kb
  • 已下载：
    0次
  • 提 供 者：
    zhang*****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

actel fusion startkit FPGA开发板试验例程，可实现2k8的双口ram，实现数据存储，缓冲。包含verilog HDL 语言源码,actel fusion startkit FPGA development board test routines, can be realized 2k8' s dual-port ram, achieving data storage, buffer. Language source code contains the verilog HDL..
(系统自动生成,下载前可以参看下载内容)

下载文件列表

dual_RAM/Project/DualPortRAM/designer/impl1/designer.log
dual_RAM/Project/DualPortRAM/designer/impl1/designer_genhdl.log
dual_RAM/Project/DualPortRAM/designer/impl1/top.adb
dual_RAM/Project/DualPortRAM/designer/impl1/top.dtf/verify.log
dual_RAM/Project/DualPortRAM/designer/impl1/top.ide_des
dual_RAM/Project/DualPortRAM/designer/impl1/top.pdb
dual_RAM/Project/DualPortRAM/designer/impl1/top.pdb.depends
dual_RAM/Project/DualPortRAM/designer/impl1/top.stp
dual_RAM/Project/DualPortRAM/designer/impl1/top.tcl
dual_RAM/Project/DualPortRAM/designer/impl1/top_fp/$$FlashPro_FPBBALTLPT1.L$$
dual_RAM/Project/DualPortRAM/designer/impl1/top_fp/projectData/top.pdb
dual_RAM/Project/DualPortRAM/designer/impl1/top_fp/top.log
dual_RAM/Project/DualPortRAM/designer/impl1/top_fp/top.pro
dual_RAM/Project/DualPortRAM/DualPortRAM.prj
dual_RAM/Project/DualPortRAM/hdl/hdlsynchk.tcl
dual_RAM/Project/DualPortRAM/hdl/rec.v
dual_RAM/Project/DualPortRAM/hdl/send.v
dual_RAM/Project/DualPortRAM/hdl/top.v
dual_RAM/Project/DualPortRAM/hdl/writeram.v
dual_RAM/Project/DualPortRAM/simulation/meminit.dat
dual_RAM/Project/DualPortRAM/simulation/modelsim.ini
dual_RAM/Project/DualPortRAM/simulation/modelsim.ini.sav
dual_RAM/Project/DualPortRAM/simulation/RAM2k8_R0C0.mem
dual_RAM/Project/DualPortRAM/simulation/RAM2k8_R0C1.mem
dual_RAM/Project/DualPortRAM/simulation/RAM2k8_R0C2.mem
dual_RAM/Project/DualPortRAM/simulation/RAM2k8_R0C3.mem
dual_RAM/Project/DualPortRAM/smartgen/RAM2k8/RAM2k8.cxf
dual_RAM/Project/DualPortRAM/smartgen/RAM2k8/RAM2k8.gen
dual_RAM/Project/DualPortRAM/smartgen/RAM2k8/RAM2k8.log
dual_RAM/Project/DualPortRAM/smartgen/RAM2k8/RAM2k8.shx
dual_RAM/Project/DualPortRAM/smartgen/RAM2k8/RAM2k8.v
dual_RAM/Project/DualPortRAM/smartgen/RAM2k8/RAM2k8_R0C0.mem
dual_RAM/Project/DualPortRAM/smartgen/RAM2k8/RAM2k8_R0C1.mem
dual_RAM/Project/DualPortRAM/smartgen/RAM2k8/RAM2k8_R0C2.mem
dual_RAM/Project/DualPortRAM/smartgen/RAM2k8/RAM2k8_R0C3.mem
dual_RAM/Project/DualPortRAM/smartgen/RAM2k8_work.ixf
dual_RAM/Project/DualPortRAM/smartgen/smartgen.aws
dual_RAM/Project/DualPortRAM/synthesis/.recordref
dual_RAM/Project/DualPortRAM/synthesis/stdout.log
dual_RAM/Project/DualPortRAM/synthesis/syntmp/sap.log
dual_RAM/Project/DualPortRAM/synthesis/syntmp/top.msg
dual_RAM/Project/DualPortRAM/synthesis/syntmp/top.plg
dual_RAM/Project/DualPortRAM/synthesis/syntmp/top_flink.htm
dual_RAM/Project/DualPortRAM/synthesis/syntmp/top_srr.htm
dual_RAM/Project/DualPortRAM/synthesis/syntmp/top_toc.htm
dual_RAM/Project/DualPortRAM/synthesis/top.areasrr
dual_RAM/Project/DualPortRAM/synthesis/top.edn
dual_RAM/Project/DualPortRAM/synthesis/top.fse
dual_RAM/Project/DualPortRAM/synthesis/top.htm
dual_RAM/Project/DualPortRAM/synthesis/top.map
dual_RAM/Project/DualPortRAM/synthesis/top.sap
dual_RAM/Project/DualPortRAM/synthesis/top.sdf
dual_RAM/Project/DualPortRAM/synthesis/top.srd
dual_RAM/Project/DualPortRAM/synthesis/top.srm
dual_RAM/Project/DualPortRAM/synthesis/top.srr
dual_RAM/Project/DualPortRAM/synthesis/top.srs
dual_RAM/Project/DualPortRAM/synthesis/top.tlg
dual_RAM/Project/DualPortRAM/synthesis/top_drc.rpt
dual_RAM/Project/DualPortRAM/synthesis/top_sdc.sdc
dual_RAM/Project/DualPortRAM/synthesis/top_syn.prj
dual_RAM/Project/DualPortRAM/synthesis/traplog.tlg
dual_RAM/Project/DualPortRAM/viewdraw/vf/project.lst
dual_RAM/Project/DualPortRAM/viewdraw/viewdraw.ini
dual_RAM/Source File/rec.v
dual_RAM/Source File/send.v
dual_RAM/Source File/top.v
dual_RAM/Source File/waveperl.log
dual_RAM/Source File/writeram.v
dual_RAM/Project/DualPortRAM/designer/impl1/top_fp/projectData
dual_RAM/Project/DualPortRAM/designer/impl1/simulation
dual_RAM/Project/DualPortRAM/designer/impl1/top.dtf
dual_RAM/Project/DualPortRAM/designer/impl1/top_fp
dual_RAM/Project/DualPortRAM/designer/impl1
dual_RAM/Project/DualPortRAM/smartgen/RAM2k8
dual_RAM/Project/DualPortRAM/synthesis/syntmp
dual_RAM/Project/DualPortRAM/viewdraw/sch
dual_RAM/Project/DualPortRAM/viewdraw/sym
dual_RAM/Project/DualPortRAM/viewdraw/vf
dual_RAM/Project/DualPortRAM/viewdraw/wir
dual_RAM/Project/DualPortRAM/component
dual_RAM/Project/DualPortRAM/constraint
dual_RAM/Project/DualPortRAM/coreconsole
dual_RAM/Project/DualPortRAM/designer
dual_RAM/Project/DualPortRAM/hdl
dual_RAM/Project/DualPortRAM/phy_synthesis
dual_RAM/Project/DualPortRAM/simulation
dual_RAM/Project/DualPortRAM/smartgen
dual_RAM/Project/DualPortRAM/stimulus
dual_RAM/Project/DualPortRAM/synthesis
dual_RAM/Project/DualPortRAM/viewdraw
dual_RAM/Project/DualPortRAM
dual_RAM/Project
dual_RAM/Source File
dual_RAM

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