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文件名称:pci.tar.gz 完成WB BUS和PCI bus之间的传输

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    2012-09-04
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    12.64mb
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verilog编写的PCI总线,提供了Wishbone bus和PCI local bus之间的接口,内由两个独立的模块组成,分别完成WB BUS和PCI bus之间的传输,The PCI IP core (PCI bridge) provides an interface between the WISHBONE SoC bus
and the PCI local bus. It consists of two independent units, one handling transactions
originating on the PCI bus, the other one handling transactions originating on the
WISHBONE bus.
相关搜索: WISHBONE pci core

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下载文件列表

pci/
pci/syn/
pci/syn/logs/
pci/syn/logs/CVS/
pci/syn/logs/CVS/Repository
pci/syn/logs/CVS/Entries
pci/syn/logs/CVS/Root
pci/syn/gate/
pci/syn/gate/CVS/
pci/syn/gate/CVS/Repository
pci/syn/gate/CVS/Entries
pci/syn/gate/CVS/Root
pci/syn/CVS/
pci/syn/CVS/Repository
pci/syn/CVS/Entries
pci/syn/CVS/Root
pci/syn/scr/
pci/syn/scr/tech_vs_umc18.inc
pci/syn/scr/analyze_design.inc
pci/syn/scr/reports.inc
pci/syn/scr/read_design.inc
pci/syn/scr/elaborate_design.inc
pci/syn/scr/cons_wb_ports.inc
pci/syn/scr/select_tech.inc
pci/syn/scr/set_env.inc
pci/syn/scr/cons_pci_ports.inc
pci/syn/scr/CVS/
pci/syn/scr/CVS/Repository
pci/syn/scr/CVS/Entries
pci/syn/scr/CVS/Root
pci/syn/scr/top_pci32.scr
pci/syn/scr/cons_art_umc18.inc
pci/syn/scr/cons_vs_umc18.inc
pci/syn/scr/save_design.inc
pci/lib/
pci/lib/README.txt
pci/lib/CVS/
pci/lib/CVS/Repository
pci/lib/CVS/Entries
pci/lib/CVS/Root
pci/sw/
pci/sw/configurator/
pci/sw/configurator/qtintf.dll
pci/sw/configurator/CVS/
pci/sw/configurator/CVS/Repository
pci/sw/configurator/CVS/Entries
pci/sw/configurator/CVS/Root
pci/sw/configurator/PCIBridgeConfig.exe
pci/sw/CVS/
pci/sw/CVS/Repository
pci/sw/CVS/Entries
pci/sw/CVS/Root
pci/sw/driver/
pci/sw/driver/fb/
pci/sw/driver/fb/CVS/
pci/sw/driver/fb/CVS/Repository
pci/sw/driver/fb/CVS/Entries
pci/sw/driver/fb/CVS/Root
pci/sw/driver/CVS/
pci/sw/driver/CVS/Repository
pci/sw/driver/CVS/Entries
pci/sw/driver/CVS/Root
pci/sim/
pci/sim/rtl_sim/
pci/sim/rtl_sim/log/
pci/sim/rtl_sim/log/parse_monitor_logs.scr
pci/sim/rtl_sim/log/pciu_mon.log
pci/sim/rtl_sim/log/ncsim.log
pci/sim/rtl_sim/log/wbu_mon.log
pci/sim/rtl_sim/log/get_log_err_war
pci/sim/rtl_sim/log/pci_tb.log
pci/sim/rtl_sim/log/ncelab_xilinx.log
pci/sim/rtl_sim/log/CVS/
pci/sim/rtl_sim/log/CVS/Repository
pci/sim/rtl_sim/log/CVS/Entries
pci/sim/rtl_sim/log/CVS/Root
pci/sim/rtl_sim/log/example_pci_tb.log
pci/sim/rtl_sim/log/ncvlog.log
pci/sim/rtl_sim/out/
pci/sim/rtl_sim/out/CVS/
pci/sim/rtl_sim/out/CVS/Repository
pci/sim/rtl_sim/out/CVS/Entries
pci/sim/rtl_sim/out/CVS/Root
pci/sim/rtl_sim/bin/
pci/sim/rtl_sim/bin/ncvlog_sim.args
pci/sim/rtl_sim/bin/ncelab.args
pci/sim/rtl_sim/bin/nc_artisan.scr
pci/sim/rtl_sim/bin/nc_xilinx_artisan.scr
pci/sim/rtl_sim/bin/ncsim.rc
pci/sim/rtl_sim/bin/nc.scr
pci/sim/rtl_sim/bin/sim_file_list.lst
pci/sim/rtl_sim/bin/ncelab_xilinx.args
pci/sim/rtl_sim/bin/hdl.var
pci/sim/rtl_sim/bin/xilinx_file_list.lst
pci/sim/rtl_sim/bin/ncsim_waves.rc
pci/sim/rtl_sim/bin/ncvlog_rtl.args
pci/sim/rtl_sim/bin/nc_xilinx.scr
pci/sim/rtl_sim/bin/ncvlog_artisan.scr
pci/sim/rtl_sim/bin/CVS/
pci/sim/rtl_sim/bin/CVS/Repository
pci/sim/rtl_sim/bin/CVS/Entries
pci/sim/rtl_sim/bin/CVS/Root
pci/sim/rtl_sim/bin/artisan_file_list.lst
pci/sim/rtl_sim/bin/vs_file_list.lst
pci/sim/rtl_sim/bin/ncsim.args
pci/sim/rtl_sim/bin/cds.lib
pci/sim/rtl_sim/bin/ncvlog_artisan.args
pci/sim/rtl_sim/bin/INCA_libs/
pci/sim/rtl_sim/bin/INCA_libs/worklib/
pci/sim/rtl_sim/bin/INCA_libs/worklib/CVS/
pci/sim/rtl_sim/bin/INCA_libs/worklib/CVS/Repository
pci/sim/rtl_sim/bin/INCA_libs/worklib/CVS/Entries
pci/sim/rtl_sim/bin/INCA_libs/worklib/CVS/Root
pci/sim/rtl_sim/bin/INCA_libs/CVS/
pci/sim/rtl_sim/bin/INCA_libs/CVS/Repository
pci/sim/rtl_sim/bin/INCA_libs/CVS/Entries
pci/sim/rtl_sim/bin/INCA_libs/CVS/Root
pci/sim/rtl_sim/bin/ncvlog_xilinx.args
pci/sim/rtl_sim/bin/rtl_file_list.lst
pci/sim/rtl_sim/bin/ncvlog_xilinx.scr
pci/sim/rtl_sim/CVS/
pci/sim/rtl_sim/CVS/Repository
pci/sim/rtl_sim/CVS/Entries
pci/sim/rtl_sim/CVS/Root
pci/sim/rtl_sim/run/
pci/sim/rtl_sim/run/ncelab.args
pci/sim/rtl_sim/run/regression_example
pci/sim/rtl_sim/run/ncsim.key
pci/sim/rtl_sim/run/top_groups.do
pci/sim/rtl_sim/run/run_pci_sim_regr.scr
pci/sim/rtl_sim/run/ncvlog.args
pci/sim/rtl_sim/run/CVS/
pci/sim/rtl_sim/run/CVS/Repository
pci/sim/rtl_sim/run/CVS/Entries
pci/sim/rtl_sim/run/CVS/Root
pci/sim/rtl_sim/run/clean
pci/sim/rtl_sim/run/ncsim.args
pci/sim/CVS/
pci/sim/CVS/Repository
pci/sim/CVS/Entries
pci/sim/CVS/Root
pci/rtl/
pci/rtl/verilog/
pci/rtl/verilog/pci_spoci_ctrl.v
pci/rtl/verilog/pci_io_mux_ad_load_crit.v
pci/rtl/verilog/pci_irdy_out_crit.v
pci/rtl/verilog/pci_frame_load_crit.v
pci/rtl/verilog/pci_delayed_write_reg.v
pci/rtl/verilog/pci_serr_en_crit.v
pci/rtl/verilog/pci_master32_sm.v
pci/rtl/verilog/pci_wbs_wbb3_2_wbb2.v
pci/rtl/verilog/pci_wb_decoder.v
pci/rtl/verilog/pci_user_constants.v
pci/rtl/verilog/pci_io_mux_ad_en_crit.v
pci/rtl/verilog/pci_delayed_sync.v
pci/rtl/verilog/pci_sync_module.v
pci/rtl/verilog/pci_cur_out_reg.v
pci/rtl/verilog/pci_async_reset_flop.v
pci/rtl/verilog/pci_target32_trdy_crit.v
pci/rtl/verilog/pci_bridge32.v
pci/rtl/verilog/pci_master32_sm_if.v
pci/rtl/verilog/pci_wbw_fifo_control.v
pci/rtl/verilog/pci_out_reg.v
pci/rtl/verilog/pci_mas_ch_state_crit.v
pci/rtl/verilog/pci_in_reg.v
pci/rtl/verilog/pci_frame_crit.v
pci/rtl/verilog/pci_conf_cyc_addr_dec.v
pci/rtl/verilog/pci_target32_devs_crit.v
pci/rtl/verilog/pci_pcir_fifo_control.v
pci/rtl/verilog/pci_wb_tpram.v
pci/rtl/verilog/pci_target_unit.v
pci/rtl/verilog/pci_wbr_fifo_control.v
pci/rtl/verilog/pci_frame_en_crit.v
pci/rtl/verilog/pci_wbw_wbr_fifos.v
pci/

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