文件名称:xilinx_fpga
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- 上传时间:2012-10-14
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文件大小:2.46mb
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赛林思fpga开发实例包括verilog语言和vhdl语言-The Sailin Si fpga development Examples include the verilog language and vhdl language
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下载文件列表
xilinx_fpga/FPGA逻辑设计实验/lab2/arwz_pace.dhp
xilinx_fpga/FPGA逻辑设计实验/lab2/arwz_pace.ise
xilinx_fpga/FPGA逻辑设计实验/lab2/arwz_pace.ise.old
xilinx_fpga/FPGA逻辑设计实验/lab2/arwz_pace.ise_8.1i_backup
xilinx_fpga/FPGA逻辑设计实验/lab2/arwz_pace.ise_ISE_Backup
xilinx_fpga/FPGA逻辑设计实验/lab2/bbfifo_16x8.vhd
xilinx_fpga/FPGA逻辑设计实验/lab2/kcpsm3.vhd
xilinx_fpga/FPGA逻辑设计实验/lab2/kcuart_rx.vhd
xilinx_fpga/FPGA逻辑设计实验/lab2/kcuart_tx.vhd
xilinx_fpga/FPGA逻辑设计实验/lab2/uart_clock.vhd
xilinx_fpga/FPGA逻辑设计实验/lab2/uart_clock_summary.html
xilinx_fpga/FPGA逻辑设计实验/lab2/uart_rx.vhd
xilinx_fpga/FPGA逻辑设计实验/lab2/uart_tx.vhd
xilinx_fpga/FPGA逻辑设计实验/lab2/UCLOCK.VHD
xilinx_fpga/FPGA逻辑设计实验/lab3/Assembler/assemble.bat
xilinx_fpga/FPGA逻辑设计实验/lab3/Assembler/CONSTANT.TXT
xilinx_fpga/FPGA逻辑设计实验/lab3/Assembler/KCPSM3.EXE
xilinx_fpga/FPGA逻辑设计实验/lab3/Assembler/LABELS.TXT
xilinx_fpga/FPGA逻辑设计实验/lab3/Assembler/PASS1.DAT
xilinx_fpga/FPGA逻辑设计实验/lab3/Assembler/PASS2.DAT
xilinx_fpga/FPGA逻辑设计实验/lab3/Assembler/PASS3.DAT
xilinx_fpga/FPGA逻辑设计实验/lab3/Assembler/PASS4.DAT
xilinx_fpga/FPGA逻辑设计实验/lab3/Assembler/PASS5.DAT
xilinx_fpga/FPGA逻辑设计实验/lab3/Assembler/PROGRAM.COE
xilinx_fpga/FPGA逻辑设计实验/lab3/Assembler/PROGRAM.DEC
xilinx_fpga/FPGA逻辑设计实验/lab3/Assembler/PROGRAM.FMT
xilinx_fpga/FPGA逻辑设计实验/lab3/Assembler/PROGRAM.HEX
xilinx_fpga/FPGA逻辑设计实验/lab3/Assembler/PROGRAM.LOG
xilinx_fpga/FPGA逻辑设计实验/lab3/Assembler/PROGRAM.M
xilinx_fpga/FPGA逻辑设计实验/lab3/Assembler/program.psm
xilinx_fpga/FPGA逻辑设计实验/lab3/Assembler/PROGRAM.V
xilinx_fpga/FPGA逻辑设计实验/lab3/Assembler/PROGRAM.VHD
xilinx_fpga/FPGA逻辑设计实验/lab3/Assembler/ROM_form.coe
xilinx_fpga/FPGA逻辑设计实验/lab3/Assembler/ROM_form.v
xilinx_fpga/FPGA逻辑设计实验/lab3/Assembler/ROM_form.vhd
xilinx_fpga/FPGA逻辑设计实验/lab3/loopback.vhd
xilinx_fpga/FPGA逻辑设计实验/lab3/testbench.vhd
xilinx_fpga/FPGA逻辑设计实验/lab3/time_const/bbfifo_16x8.vhd
xilinx_fpga/FPGA逻辑设计实验/lab3/time_const/isim.hdlsourcefiles
xilinx_fpga/FPGA逻辑设计实验/lab3/time_const/isim.log
xilinx_fpga/FPGA逻辑设计实验/lab3/time_const/isim.tmp_save/_1
xilinx_fpga/FPGA逻辑设计实验/lab3/time_const/isimwavedata.xwv
xilinx_fpga/FPGA逻辑设计实验/lab3/time_const/kcpsm3.vhd
xilinx_fpga/FPGA逻辑设计实验/lab3/time_const/kcuart_rx.vhd
xilinx_fpga/FPGA逻辑设计实验/lab3/time_const/kcuart_tx.vhd
xilinx_fpga/FPGA逻辑设计实验/lab3/time_const/loopback.vhd
xilinx_fpga/FPGA逻辑设计实验/lab3/time_const/loopback_summary.html
xilinx_fpga/FPGA逻辑设计实验/lab3/time_const/my_dcm.xaw
xilinx_fpga/FPGA逻辑设计实验/lab3/time_const/Project.dhp
xilinx_fpga/FPGA逻辑设计实验/lab3/time_const/time_const.dhp
xilinx_fpga/FPGA逻辑设计实验/lab3/time_const/time_const.ise
xilinx_fpga/FPGA逻辑设计实验/lab3/time_const/time_const.ise.old
xilinx_fpga/FPGA逻辑设计实验/lab3/time_const/time_const.ise_8.1i_backup
xilinx_fpga/FPGA逻辑设计实验/lab3/time_const/time_const.ise_ISE_Backup
xilinx_fpga/FPGA逻辑设计实验/lab3/time_const/uart_rx.vhd
xilinx_fpga/FPGA逻辑设计实验/lab3/time_const/uart_tx.vhd
xilinx_fpga/FPGA逻辑设计实验/lab3/time_const/_xmsgs/fuse.xmsgs
xilinx_fpga/FPGA逻辑设计实验/lab3/time_const/_xmsgs/vhpcomp.xmsgs
xilinx_fpga/FPGA逻辑设计实验/lab4/Assembler/CONSTANT.TXT
xilinx_fpga/FPGA逻辑设计实验/lab4/Assembler/KCPSM3.EXE
xilinx_fpga/FPGA逻辑设计实验/lab4/Assembler/LABELS.TXT
xilinx_fpga/FPGA逻辑设计实验/lab4/Assembler/PASS1.DAT
xilinx_fpga/FPGA逻辑设计实验/lab4/Assembler/PASS2.DAT
xilinx_fpga/FPGA逻辑设计实验/lab4/Assembler/PASS3.DAT
xilinx_fpga/FPGA逻辑设计实验/lab4/Assembler/PASS4.DAT
xilinx_fpga/FPGA逻辑设计实验/lab4/Assembler/PASS5.DAT
xilinx_fpga/FPGA逻辑设计实验/lab4/Assembler/PROGRAM.COE
xilinx_fpga/FPGA逻辑设计实验/lab4/Assembler/PROGRAM.DEC
xilinx_fpga/FPGA逻辑设计实验/lab4/Assembler/PROGRAM.FMT
xilinx_fpga/FPGA逻辑设计实验/lab4/Assembler/PROGRAM.HEX
xilinx_fpga/FPGA逻辑设计实验/lab4/Assembler/PROGRAM.LOG
xilinx_fpga/FPGA逻辑设计实验/lab4/Assembler/PROGRAM.M
xilinx_fpga/FPGA逻辑设计实验/lab4/Assembler/program.psm
xilinx_fpga/FPGA逻辑设计实验/lab4/Assembler/PROGRAM.V
xilinx_fpga/FPGA逻辑设计实验/lab4/Assembler/PROGRAM.VHD
xilinx_fpga/FPGA逻辑设计实验/lab4/Assembler/ROM_form.coe
xilinx_fpga/FPGA逻辑设计实验/lab4/Assembler/ROM_form.v
xilinx_fpga/FPGA逻辑设计实验/lab4/Assembler/ROM_form.vhd
xilinx_fpga/FPGA逻辑设计实验/lab4/synth_lab/bbfifo_16x8.vhd
xilinx_fpga/FPGA逻辑设计实验/lab4/synth_lab/kcpsm3.vhd
xilinx_fpga/FPGA逻辑设计实验/lab4/synth_lab/kcuart_rx.vhd
xilinx_fpga/FPGA逻辑设计实验/lab4/synth_lab/kcuart_tx.vhd
xilinx_fpga/FPGA逻辑设计实验/lab4/synth_lab/loopback.ucf
xilinx_fpga/FPGA逻辑设计实验/lab4/synth_lab/loopback.ut
xilinx_fpga/FPGA逻辑设计实验/lab4/synth_lab/loopback.vhd
xilinx_fpga/FPGA逻辑设计实验/lab4/synth_lab/loopback_prev_built.ngd
xilinx_fpga/FPGA逻辑设计实验/lab4/synth_lab/loopback_summary.html
xilinx_fpga/FPGA逻辑设计实验/lab4/synth_lab/my_dcm.xaw
xilinx_fpga/FPGA逻辑设计实验/lab4/synth_lab/synth_lab.ise
xilinx_fpga/FPGA逻辑设计实验/lab4/synth_lab/synth_lab.ise_ISE_Backup
xilinx_fpga/FPGA逻辑设计实验/lab4/synth_lab/synth_lab.ntrc_log
xilinx_fpga/FPGA逻辑设计实验/lab4/synth_lab/testbench.vhd
xilinx_fpga/FPGA逻辑设计实验/lab4/synth_lab/uart_rx.vhd
xilinx_fpga/FPGA逻辑设计实验/lab4/synth_lab/uart_tx.vhd
xilinx_fpga/FPGA逻辑设计实验/lab4/synth_lab/_impact.cmd
xilinx_fpga/FPGA逻辑设计实验/lab4/synth_lab/_impact.log
xilinx_fpga/FPGA逻辑设计实验/lab5/Assembler/CONSTANT.TXT
xilinx_fpga/FPGA逻辑设计实验/lab5/Assembler/KCPSM3.EXE
xilinx_fpga/FPGA逻辑设计实验/lab5/Assembler/LABELS.TXT
xilinx_fpga/FPGA逻辑设计实验/lab5/Assembler/PASS1.DAT
xilinx_fpga/FPGA逻辑设计实验/lab5/Assembler/PASS2.DAT
xilinx_fpga/FPGA逻辑设计实验/lab5/Assembler
xilinx_fpga/FPGA逻辑设计实验/lab2/arwz_pace.ise
xilinx_fpga/FPGA逻辑设计实验/lab2/arwz_pace.ise.old
xilinx_fpga/FPGA逻辑设计实验/lab2/arwz_pace.ise_8.1i_backup
xilinx_fpga/FPGA逻辑设计实验/lab2/arwz_pace.ise_ISE_Backup
xilinx_fpga/FPGA逻辑设计实验/lab2/bbfifo_16x8.vhd
xilinx_fpga/FPGA逻辑设计实验/lab2/kcpsm3.vhd
xilinx_fpga/FPGA逻辑设计实验/lab2/kcuart_rx.vhd
xilinx_fpga/FPGA逻辑设计实验/lab2/kcuart_tx.vhd
xilinx_fpga/FPGA逻辑设计实验/lab2/uart_clock.vhd
xilinx_fpga/FPGA逻辑设计实验/lab2/uart_clock_summary.html
xilinx_fpga/FPGA逻辑设计实验/lab2/uart_rx.vhd
xilinx_fpga/FPGA逻辑设计实验/lab2/uart_tx.vhd
xilinx_fpga/FPGA逻辑设计实验/lab2/UCLOCK.VHD
xilinx_fpga/FPGA逻辑设计实验/lab3/Assembler/assemble.bat
xilinx_fpga/FPGA逻辑设计实验/lab3/Assembler/CONSTANT.TXT
xilinx_fpga/FPGA逻辑设计实验/lab3/Assembler/KCPSM3.EXE
xilinx_fpga/FPGA逻辑设计实验/lab3/Assembler/LABELS.TXT
xilinx_fpga/FPGA逻辑设计实验/lab3/Assembler/PASS1.DAT
xilinx_fpga/FPGA逻辑设计实验/lab3/Assembler/PASS2.DAT
xilinx_fpga/FPGA逻辑设计实验/lab3/Assembler/PASS3.DAT
xilinx_fpga/FPGA逻辑设计实验/lab3/Assembler/PASS4.DAT
xilinx_fpga/FPGA逻辑设计实验/lab3/Assembler/PASS5.DAT
xilinx_fpga/FPGA逻辑设计实验/lab3/Assembler/PROGRAM.COE
xilinx_fpga/FPGA逻辑设计实验/lab3/Assembler/PROGRAM.DEC
xilinx_fpga/FPGA逻辑设计实验/lab3/Assembler/PROGRAM.FMT
xilinx_fpga/FPGA逻辑设计实验/lab3/Assembler/PROGRAM.HEX
xilinx_fpga/FPGA逻辑设计实验/lab3/Assembler/PROGRAM.LOG
xilinx_fpga/FPGA逻辑设计实验/lab3/Assembler/PROGRAM.M
xilinx_fpga/FPGA逻辑设计实验/lab3/Assembler/program.psm
xilinx_fpga/FPGA逻辑设计实验/lab3/Assembler/PROGRAM.V
xilinx_fpga/FPGA逻辑设计实验/lab3/Assembler/PROGRAM.VHD
xilinx_fpga/FPGA逻辑设计实验/lab3/Assembler/ROM_form.coe
xilinx_fpga/FPGA逻辑设计实验/lab3/Assembler/ROM_form.v
xilinx_fpga/FPGA逻辑设计实验/lab3/Assembler/ROM_form.vhd
xilinx_fpga/FPGA逻辑设计实验/lab3/loopback.vhd
xilinx_fpga/FPGA逻辑设计实验/lab3/testbench.vhd
xilinx_fpga/FPGA逻辑设计实验/lab3/time_const/bbfifo_16x8.vhd
xilinx_fpga/FPGA逻辑设计实验/lab3/time_const/isim.hdlsourcefiles
xilinx_fpga/FPGA逻辑设计实验/lab3/time_const/isim.log
xilinx_fpga/FPGA逻辑设计实验/lab3/time_const/isim.tmp_save/_1
xilinx_fpga/FPGA逻辑设计实验/lab3/time_const/isimwavedata.xwv
xilinx_fpga/FPGA逻辑设计实验/lab3/time_const/kcpsm3.vhd
xilinx_fpga/FPGA逻辑设计实验/lab3/time_const/kcuart_rx.vhd
xilinx_fpga/FPGA逻辑设计实验/lab3/time_const/kcuart_tx.vhd
xilinx_fpga/FPGA逻辑设计实验/lab3/time_const/loopback.vhd
xilinx_fpga/FPGA逻辑设计实验/lab3/time_const/loopback_summary.html
xilinx_fpga/FPGA逻辑设计实验/lab3/time_const/my_dcm.xaw
xilinx_fpga/FPGA逻辑设计实验/lab3/time_const/Project.dhp
xilinx_fpga/FPGA逻辑设计实验/lab3/time_const/time_const.dhp
xilinx_fpga/FPGA逻辑设计实验/lab3/time_const/time_const.ise
xilinx_fpga/FPGA逻辑设计实验/lab3/time_const/time_const.ise.old
xilinx_fpga/FPGA逻辑设计实验/lab3/time_const/time_const.ise_8.1i_backup
xilinx_fpga/FPGA逻辑设计实验/lab3/time_const/time_const.ise_ISE_Backup
xilinx_fpga/FPGA逻辑设计实验/lab3/time_const/uart_rx.vhd
xilinx_fpga/FPGA逻辑设计实验/lab3/time_const/uart_tx.vhd
xilinx_fpga/FPGA逻辑设计实验/lab3/time_const/_xmsgs/fuse.xmsgs
xilinx_fpga/FPGA逻辑设计实验/lab3/time_const/_xmsgs/vhpcomp.xmsgs
xilinx_fpga/FPGA逻辑设计实验/lab4/Assembler/CONSTANT.TXT
xilinx_fpga/FPGA逻辑设计实验/lab4/Assembler/KCPSM3.EXE
xilinx_fpga/FPGA逻辑设计实验/lab4/Assembler/LABELS.TXT
xilinx_fpga/FPGA逻辑设计实验/lab4/Assembler/PASS1.DAT
xilinx_fpga/FPGA逻辑设计实验/lab4/Assembler/PASS2.DAT
xilinx_fpga/FPGA逻辑设计实验/lab4/Assembler/PASS3.DAT
xilinx_fpga/FPGA逻辑设计实验/lab4/Assembler/PASS4.DAT
xilinx_fpga/FPGA逻辑设计实验/lab4/Assembler/PASS5.DAT
xilinx_fpga/FPGA逻辑设计实验/lab4/Assembler/PROGRAM.COE
xilinx_fpga/FPGA逻辑设计实验/lab4/Assembler/PROGRAM.DEC
xilinx_fpga/FPGA逻辑设计实验/lab4/Assembler/PROGRAM.FMT
xilinx_fpga/FPGA逻辑设计实验/lab4/Assembler/PROGRAM.HEX
xilinx_fpga/FPGA逻辑设计实验/lab4/Assembler/PROGRAM.LOG
xilinx_fpga/FPGA逻辑设计实验/lab4/Assembler/PROGRAM.M
xilinx_fpga/FPGA逻辑设计实验/lab4/Assembler/program.psm
xilinx_fpga/FPGA逻辑设计实验/lab4/Assembler/PROGRAM.V
xilinx_fpga/FPGA逻辑设计实验/lab4/Assembler/PROGRAM.VHD
xilinx_fpga/FPGA逻辑设计实验/lab4/Assembler/ROM_form.coe
xilinx_fpga/FPGA逻辑设计实验/lab4/Assembler/ROM_form.v
xilinx_fpga/FPGA逻辑设计实验/lab4/Assembler/ROM_form.vhd
xilinx_fpga/FPGA逻辑设计实验/lab4/synth_lab/bbfifo_16x8.vhd
xilinx_fpga/FPGA逻辑设计实验/lab4/synth_lab/kcpsm3.vhd
xilinx_fpga/FPGA逻辑设计实验/lab4/synth_lab/kcuart_rx.vhd
xilinx_fpga/FPGA逻辑设计实验/lab4/synth_lab/kcuart_tx.vhd
xilinx_fpga/FPGA逻辑设计实验/lab4/synth_lab/loopback.ucf
xilinx_fpga/FPGA逻辑设计实验/lab4/synth_lab/loopback.ut
xilinx_fpga/FPGA逻辑设计实验/lab4/synth_lab/loopback.vhd
xilinx_fpga/FPGA逻辑设计实验/lab4/synth_lab/loopback_prev_built.ngd
xilinx_fpga/FPGA逻辑设计实验/lab4/synth_lab/loopback_summary.html
xilinx_fpga/FPGA逻辑设计实验/lab4/synth_lab/my_dcm.xaw
xilinx_fpga/FPGA逻辑设计实验/lab4/synth_lab/synth_lab.ise
xilinx_fpga/FPGA逻辑设计实验/lab4/synth_lab/synth_lab.ise_ISE_Backup
xilinx_fpga/FPGA逻辑设计实验/lab4/synth_lab/synth_lab.ntrc_log
xilinx_fpga/FPGA逻辑设计实验/lab4/synth_lab/testbench.vhd
xilinx_fpga/FPGA逻辑设计实验/lab4/synth_lab/uart_rx.vhd
xilinx_fpga/FPGA逻辑设计实验/lab4/synth_lab/uart_tx.vhd
xilinx_fpga/FPGA逻辑设计实验/lab4/synth_lab/_impact.cmd
xilinx_fpga/FPGA逻辑设计实验/lab4/synth_lab/_impact.log
xilinx_fpga/FPGA逻辑设计实验/lab5/Assembler/CONSTANT.TXT
xilinx_fpga/FPGA逻辑设计实验/lab5/Assembler/KCPSM3.EXE
xilinx_fpga/FPGA逻辑设计实验/lab5/Assembler/LABELS.TXT
xilinx_fpga/FPGA逻辑设计实验/lab5/Assembler/PASS1.DAT
xilinx_fpga/FPGA逻辑设计实验/lab5/Assembler/PASS2.DAT
xilinx_fpga/FPGA逻辑设计实验/lab5/Assembler
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