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文件名称:edk_for_busy_people

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [C/C++] [源码]
  • 上传时间：
    2012-10-18
  • 文件大小：
    2.31mb
  • 已下载：
    0次
  • 提 供 者：
    se***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

XILINX 出品 EDK快速学习资料。 EDK在 Xilinx FPGA上构架一个CPU软核， 以提高整个系统的灵活性，和可扩展性。-EDK document by Xilinx.　EDK is used to build a soft CPU Core on XILINX FPGA.
相关搜索： edk xilinx FPGA xilinx edk vhdl xilinx FPGA fpga edk vhdl xilinx edk_for_busy_people edk xilinx

(系统自动生成,下载前可以参看下载内容)

下载文件列表

EDK_for_Busy_People/integrate_my_ip_w_platgen.doc
EDK_for_Busy_People/lab2/
EDK_for_Busy_People/lab2/sim.do
EDK_for_Busy_People/lab2/system.mhs
EDK_for_Busy_People/lab2/system.mss
EDK_for_Busy_People/lab2/system.mvs
EDK_for_Busy_People/lab2/system.xmp
EDK_for_Busy_People/lab2/myip/
EDK_for_Busy_People/lab2/myip/bram_block_v1_00_a/
EDK_for_Busy_People/lab2/myip/bram_block_v1_00_a/hdl/
EDK_for_Busy_People/lab2/myip/bram_block_v1_00_a/hdl/vhdl/
EDK_for_Busy_People/lab2/myip/bram_block_v1_00_a/hdl/vhdl/bram1_elaborate.vhd
EDK_for_Busy_People/lab2/myip/bram_block_v1_00_a/hdl/vhdl/bram2_elaborate.vhd
EDK_for_Busy_People/lab2/lab2_golden/
EDK_for_Busy_People/lab2/lab2_golden/download.bit
EDK_for_Busy_People/lab2/etc/
EDK_for_Busy_People/lab2/etc/bitgen.opt
EDK_for_Busy_People/lab2/etc/bitgen.ut
EDK_for_Busy_People/lab2/etc/download.cmd
EDK_for_Busy_People/lab2/etc/fast_runtime.opt
EDK_for_Busy_People/lab2/etc/lab2_golden.cmd
EDK_for_Busy_People/lab2/etc/xc18v04_vq44.bsd
EDK_for_Busy_People/lab2/data/
EDK_for_Busy_People/lab2/data/system.ucf
EDK_for_Busy_People/lab2/code/
EDK_for_Busy_People/lab2/code/hello.c
EDK_for_Busy_People/lab2/code/linker_script
EDK_for_Busy_People/lab2/code/timer_interrupt.c
EDK_for_Busy_People/lab3/
EDK_for_Busy_People/lab3/sim.do
EDK_for_Busy_People/lab3/system.make
EDK_for_Busy_People/lab3/system.mhs
EDK_for_Busy_People/lab3/system.mss
EDK_for_Busy_People/lab3/system.mvs
EDK_for_Busy_People/lab3/system.xmp
EDK_for_Busy_People/lab3/xps.cmd
EDK_for_Busy_People/lab3/myip/
EDK_for_Busy_People/lab3/myip/bram_block_v1_00_a/
EDK_for_Busy_People/lab3/myip/bram_block_v1_00_a/hdl/
EDK_for_Busy_People/lab3/myip/bram_block_v1_00_a/hdl/vhdl/
EDK_for_Busy_People/lab3/myip/bram_block_v1_00_a/hdl/vhdl/bram1_elaborate.vhd
EDK_for_Busy_People/lab3/myip/bram_block_v1_00_a/hdl/vhdl/bram2_elaborate.vhd
EDK_for_Busy_People/lab3/etc/
EDK_for_Busy_People/lab3/etc/bitgen.opt
EDK_for_Busy_People/lab3/etc/bitgen.ut
EDK_for_Busy_People/lab3/etc/download.cmd
EDK_for_Busy_People/lab3/etc/fast_runtime.opt
EDK_for_Busy_People/lab3/etc/xc18v04_vq44.bsd
EDK_for_Busy_People/lab3/data/
EDK_for_Busy_People/lab3/data/system.ucf
EDK_for_Busy_People/lab3/code/
EDK_for_Busy_People/lab3/code/linker_script
EDK_for_Busy_People/lab3/code/system.c
EDK_for_Busy_People/lab4/
EDK_for_Busy_People/lab4/system.bmm
EDK_for_Busy_People/lab4/system.log
EDK_for_Busy_People/lab4/system.make
EDK_for_Busy_People/lab4/system.mhs
EDK_for_Busy_People/lab4/system.mss
EDK_for_Busy_People/lab4/system.mvs
EDK_for_Busy_People/lab4/system.xmp
EDK_for_Busy_People/lab4/xps.cmd
EDK_for_Busy_People/lab4/myip/
EDK_for_Busy_People/lab4/myip/jtagppc_cntlr_v1_00_a/
EDK_for_Busy_People/lab4/myip/jtagppc_cntlr_v1_00_a/hdl/
EDK_for_Busy_People/lab4/myip/jtagppc_cntlr_v1_00_a/hdl/vhdl/
EDK_for_Busy_People/lab4/myip/jtagppc_cntlr_v1_00_a/hdl/vhdl/jtagppc_cntlr.vhd
EDK_for_Busy_People/lab4/myip/jtagppc_cntlr_v1_00_a/hdl/verilog/
EDK_for_Busy_People/lab4/myip/jtagppc_cntlr_v1_00_a/hdl/verilog/jtagppc_cntlr.v
EDK_for_Busy_People/lab4/myip/jtagppc_cntlr_v1_00_a/data/
EDK_for_Busy_People/lab4/myip/jtagppc_cntlr_v1_00_a/data/jtagppc_cntlr_v2_0_0.mpd
EDK_for_Busy_People/lab4/myip/jtagppc_cntlr_v1_00_a/data/jtagppc_cntlr_v2_0_0.pao
EDK_for_Busy_People/lab4/myip/ddr_clock_module_ref_v1_00_a/
EDK_for_Busy_People/lab4/myip/ddr_clock_module_ref_v1_00_a/hdl/
EDK_for_Busy_People/lab4/myip/ddr_clock_module_ref_v1_00_a/hdl/vhdl/
EDK_for_Busy_People/lab4/myip/ddr_clock_module_ref_v1_00_a/hdl/vhdl/ddr_clock_module_ref.vhd
EDK_for_Busy_People/lab4/myip/ddr_clock_module_ref_v1_00_a/data/
EDK_for_Busy_People/lab4/myip/ddr_clock_module_ref_v1_00_a/data/ddr_clock_module_ref_v2_0_0.mpd
EDK_for_Busy_People/lab4/myip/ddr_clock_module_ref_v1_00_a/data/ddr_clock_module_ref_v2_0_0.pao
EDK_for_Busy_People/lab4/myip/dcm_ip/
EDK_for_Busy_People/lab4/myip/dcm_ip/hdl/
EDK_for_Busy_People/lab4/myip/dcm_ip/hdl/vhdl/
EDK_for_Busy_People/lab4/myip/dcm_ip/hdl/vhdl/dcm_ip.vhd
EDK_for_Busy_People/lab4/myip/dcm_ip/data/
EDK_for_Busy_People/lab4/myip/dcm_ip/data/dcm_ip_v2_0_0.mpd
EDK_for_Busy_People/lab4/myip/dcm_ip/data/dcm_ip_v2_0_0.mpd~
EDK_for_Busy_People/lab4/myip/dcm_ip/data/dcm_ip_v2_0_0.pao
EDK_for_Busy_People/lab4/myip/bram_block_v1_00_a/
EDK_for_Busy_People/lab4/myip/bram_block_v1_00_a/hdl/
EDK_for_Busy_People/lab4/myip/bram_block_v1_00_a/hdl/vhdl/
EDK_for_Busy_People/lab4/myip/bram_block_v1_00_a/hdl/vhdl/bram1_elaborate.vhd
EDK_for_Busy_People/lab4/etc/
EDK_for_Busy_People/lab4/etc/bitgen.opt
EDK_for_Busy_People/lab4/etc/bitgen.ut
EDK_for_Busy_People/lab4/etc/download.cmd
EDK_for_Busy_People/lab4/etc/fast_runtime.opt
EDK_for_Busy_People/lab4/etc/system.mss
EDK_for_Busy_People/lab4/etc/xc18v04_vq44.bsd
EDK_for_Busy_People/lab4/etc/xccace.bsd
EDK_for_Busy_People/lab4/etc/_impact.cmd
EDK_for_Busy_People/lab4/etc/_impact.log
EDK_for_Busy_People/lab4/data/
EDK_for_Busy_People/lab4/data/libgen.opt
EDK_for_Busy_People/lab4/data/platgen.opt
EDK_for_Busy_People/lab4/data/simgen.opt
EDK_for_Busy_People/lab4/data/system.make
EDK_for_Busy_People/lab4/data/system.mhs
EDK_for_Busy_People/lab4/data/system.mss
EDK_for_Busy_People/l

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