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文件名称:DDR_SDRAM

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [PDF]
  • 上传时间：
    2012-10-21
  • 文件大小：
    8.09mb
  • 已下载：
    0次
  • 提 供 者：
    熊***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

ddr sdram 的控制程序，lattice的，比较好用的，大家-ddr sdram control program, lattice, and relatively easy to use, and we look
相关搜索： sdram lattice DDR SDRAM lattice lattice fpga vhdl sdram ddr sdram demo lattice

(系统自动生成,下载前可以参看下载内容)

下载文件列表

DDR SDRAM/4_01_02_04R13.pdf
DDR SDRAM/DDR SDRAM/mem_interface_top.txt
DDR SDRAM/DDR SDRAM/mem_interface_top_addr_gen_0.txt
DDR SDRAM/DDR SDRAM/mem_interface_top_backend_fifos_0.txt
DDR SDRAM/DDR SDRAM/mem_interface_top_backend_rom_0.txt
DDR SDRAM/DDR SDRAM/mem_interface_top_cmp_rd_data_0.txt
DDR SDRAM/DDR SDRAM/mem_interface_top_controller_iobs_0.txt
DDR SDRAM/DDR SDRAM/mem_interface_top_data_gen_16.txt
DDR SDRAM/DDR SDRAM/mem_interface_top_data_path_0.txt
DDR SDRAM/DDR SDRAM/mem_interface_top_data_path_iobs_0.txt
DDR SDRAM/DDR SDRAM/mem_interface_top_data_tap_inc.txt
DDR SDRAM/DDR SDRAM/mem_interface_top_data_write_0.txt
DDR SDRAM/DDR SDRAM/mem_interface_top_ddr_controller_0.txt
DDR SDRAM/DDR SDRAM/mem_interface_top_idelay_ctrl.txt
DDR SDRAM/DDR SDRAM/mem_interface_top_infrastructure.txt
DDR SDRAM/DDR SDRAM/mem_interface_top_infrastructure_iobs_0.txt
DDR SDRAM/DDR SDRAM/mem_interface_top_iobs_0.txt
DDR SDRAM/DDR SDRAM/mem_interface_top_main_0.txt
DDR SDRAM/DDR SDRAM/mem_interface_top_parameters_0.txt
DDR SDRAM/DDR SDRAM/mem_interface_top_pattern_compare8.txt
DDR SDRAM/DDR SDRAM/mem_interface_top_RAM_D_0.txt
DDR SDRAM/DDR SDRAM/mem_interface_top_rd_data_0.txt
DDR SDRAM/DDR SDRAM/mem_interface_top_rd_data_fifo_0.txt
DDR SDRAM/DDR SDRAM/mem_interface_top_rd_wr_addr_fifo_0.txt
DDR SDRAM/DDR SDRAM/mem_interface_top_tap_ctrl_0.txt
DDR SDRAM/DDR SDRAM/mem_interface_top_tap_logic_0.txt
DDR SDRAM/DDR SDRAM/mem_interface_top_test_bench_0.txt
DDR SDRAM/DDR SDRAM/mem_interface_top_top_0.txt
DDR SDRAM/DDR SDRAM/mem_interface_top_user_interface_0.txt
DDR SDRAM/DDR SDRAM/mem_interface_top_v4_dm_iob.txt
DDR SDRAM/DDR SDRAM/mem_interface_top_v4_dqs_iob.txt
DDR SDRAM/DDR SDRAM/mem_interface_top_v4_dq_iob.txt
DDR SDRAM/DDR SDRAM/mem_interface_top_wr_data_fifo_16.txt
DDR SDRAM/DDR SDRAM/使用 Virtex-4 FPGA 器件实现DDR SDRAM控制器.pdf
DDR SDRAM/DDR SDRAM控制器的FPGA实现.pdf
DDR SDRAM/DDR SDRAM设计及调试经验总结.pdf
DDR SDRAM/DDR System Design Considerations.pdf
DDR SDRAM/ddrregrev1.2.pdf
DDR SDRAM/DDR_SDRAM_controller/doc/ddr_sdram.pdf
DDR SDRAM/DDR_SDRAM_controller/help.txt
DDR SDRAM/DDR_SDRAM_controller/model/mt46v4m16.vhd
DDR SDRAM/DDR_SDRAM_controller/model/mti_pkg.vhd
DDR SDRAM/DDR_SDRAM_controller/PCB资源网.txt
DDR SDRAM/DDR_SDRAM_controller/route/ddr_sdram.csf
DDR SDRAM/DDR_SDRAM_controller/route/ddr_sdram.esf
DDR SDRAM/DDR_SDRAM_controller/route/ddr_sdram.quartus
DDR SDRAM/DDR_SDRAM_controller/route/ddr_sdram.vqm
DDR SDRAM/DDR_SDRAM_controller/route/pll1.vhd
DDR SDRAM/DDR_SDRAM_controller/simulation/APEX20KE_MF.VHD
DDR SDRAM/DDR_SDRAM_controller/simulation/ddr_command.vhd
DDR SDRAM/DDR_SDRAM_controller/simulation/ddr_control_interface.vhd
DDR SDRAM/DDR_SDRAM_controller/simulation/ddr_data_path.vhd
DDR SDRAM/DDR_SDRAM_controller/simulation/ddr_sdram.vhd
DDR SDRAM/DDR_SDRAM_controller/simulation/ddr_sdram_tb.vhd
DDR SDRAM/DDR_SDRAM_controller/simulation/io_utils.vhd
DDR SDRAM/DDR_SDRAM_controller/simulation/lpm_pack.vhd
DDR SDRAM/DDR_SDRAM_controller/simulation/modelsim.ini
DDR SDRAM/DDR_SDRAM_controller/simulation/mt46v4m16.vhd
DDR SDRAM/DDR_SDRAM_controller/simulation/mti_pkg.bak
DDR SDRAM/DDR_SDRAM_controller/simulation/mti_pkg.vhd
DDR SDRAM/DDR_SDRAM_controller/simulation/pll1.vhd
DDR SDRAM/DDR_SDRAM_controller/simulation/readme.txt
DDR SDRAM/DDR_SDRAM_controller/simulation/stdlogar.vhd
DDR SDRAM/DDR_SDRAM_controller/simulation/util1164.vhd
DDR SDRAM/DDR_SDRAM_controller/simulation/wave.do
DDR SDRAM/DDR_SDRAM_controller/simulation/work/altcam/behave.dat
DDR SDRAM/DDR_SDRAM_controller/simulation/work/altcam/behave.psm
DDR SDRAM/DDR_SDRAM_controller/simulation/work/altcam/_primary.dat
DDR SDRAM/DDR_SDRAM_controller/simulation/work/altclklock/behavior.dat
DDR SDRAM/DDR_SDRAM_controller/simulation/work/altclklock/behavior.psm
DDR SDRAM/DDR_SDRAM_controller/simulation/work/altclklock/_primary.dat
DDR SDRAM/DDR_SDRAM_controller/simulation/work/altlvds_rx/behavior.dat
DDR SDRAM/DDR_SDRAM_controller/simulation/work/altlvds_rx/behavior.psm
DDR SDRAM/DDR_SDRAM_controller/simulation/work/altlvds_rx/_primary.dat
DDR SDRAM/DDR_SDRAM_controller/simulation/work/altlvds_tx/behavior.dat
DDR SDRAM/DDR_SDRAM_controller/simulation/work/altlvds_tx/behavior.psm
DDR SDRAM/DDR_SDRAM_controller/simulation/work/altlvds_tx/_primary.dat
DDR SDRAM/DDR_SDRAM_controller/simulation/work/command/rtl.dat
DDR SDRAM/DDR_SDRAM_controller/simulation/work/command/rtl.psm
DDR SDRAM/DDR_SDRAM_controller/simulation/work/command/_primary.dat
DDR SDRAM/DDR_SDRAM_controller/simulation/work/control_interface/rtl.dat
DDR SDRAM/DDR_SDRAM_controller/simulation/work/control_interface/rtl.psm
DDR SDRAM/DDR_SDRAM_controller/simulation/work/control_interface/_primary.dat
DDR SDRAM/DDR_SDRAM_controller/simulation/work/ddr_command/rtl.dat
DDR SDRAM/DDR_SDRAM_controller/simulation/work/ddr_command/rtl.psm
DDR SDRAM/DDR_SDRAM_controller/simulation/work/ddr_command/_primary.dat
DDR SDRAM/DDR_SDRAM_controller/simulation/work/ddr_control_interface/rtl.dat
DDR SDRAM/DDR_SDRAM_controller/simulation/work/ddr_control_interface/rtl.psm
DDR SDRAM/DDR_SDRAM_controller/simulation/work/ddr_control_interface/_primary.dat
DDR SDRAM

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