CPLD_SPI
CPLD_SPI/6a26531a-afd2-4517-a09b-1780b91fc30e.rar
CPLD_SPI/an485_CN.pdf
CPLD_SPI/an485_design_example.zip
CPLD_SPI/detail384641.htm
CPLD_SPI/基于CPLD的SPI总线试验简单程序 - forever的日志 - 网易博客.mht
CPLD_SPI/基于CPLD的SPI总线试验简单程序【转】 - wenstar的个人空间 - 电子工程世界 - Powered by X-Space.mht
CPLD_SPI/6a26531a-afd2-4517-a09b-1780b91fc30e
CPLD_SPI/6a26531a-afd2-4517-a09b-1780b91fc30e/ModelSim_ tb_spi().pdf
CPLD_SPI/6a26531a-afd2-4517-a09b-1780b91fc30e/spi.v
CPLD_SPI/an485_design_example
CPLD_SPI/an485_design_example/code
CPLD_SPI/an485_design_example/code/SPI_Master.v
CPLD_SPI/an485_design_example/modelsim
CPLD_SPI/an485_design_example/modelsim/SPI_Master.cr.mti
CPLD_SPI/an485_design_example/modelsim/SPI_Master.mpf
CPLD_SPI/an485_design_example/modelsim/SPI_Master.v
CPLD_SPI/an485_design_example/modelsim/SPI_Master_test.v
CPLD_SPI/an485_design_example/modelsim/SPI_Master_test.v.bak
CPLD_SPI/an485_design_example/modelsim/transcript
CPLD_SPI/an485_design_example/modelsim/vsim.wlf
CPLD_SPI/an485_design_example/modelsim/wave.bmp
CPLD_SPI/an485_design_example/modelsim/wave.do
CPLD_SPI/an485_design_example/modelsim/work
CPLD_SPI/an485_design_example/modelsim/work/_info
CPLD_SPI/an485_design_example/modelsim/work/@s@p@i_@master
CPLD_SPI/an485_design_example/modelsim/work/@s@p@i_@master/verilog.psm
CPLD_SPI/an485_design_example/modelsim/work/@s@p@i_@master/_primary.dat
CPLD_SPI/an485_design_example/modelsim/work/@s@p@i_@master/_primary.vhd
CPLD_SPI/an485_design_example/modelsim/work/@s@p@i_master_test
CPLD_SPI/an485_design_example/modelsim/work/@s@p@i_master_test/verilog.psm
CPLD_SPI/an485_design_example/modelsim/work/@s@p@i_master_test/_primary.dat
CPLD_SPI/an485_design_example/modelsim/work/@s@p@i_master_test/_primary.vhd
CPLD_SPI/an485_design_example/quartus
CPLD_SPI/an485_design_example/quartus/SPI_Master.asm.rpt
CPLD_SPI/an485_design_example/quartus/SPI_Master.done
CPLD_SPI/an485_design_example/quartus/SPI_Master.dpf
CPLD_SPI/an485_design_example/quartus/SPI_Master.fit.rpt
CPLD_SPI/an485_design_example/quartus/SPI_Master.fit.smsg
CPLD_SPI/an485_design_example/quartus/SPI_Master.fit.summary
CPLD_SPI/an485_design_example/quartus/SPI_Master.flow.rpt
CPLD_SPI/an485_design_example/quartus/SPI_Master.map.rpt
CPLD_SPI/an485_design_example/quartus/SPI_Master.map.smsg
CPLD_SPI/an485_design_example/quartus/SPI_Master.map.summary
CPLD_SPI/an485_design_example/quartus/SPI_Master.pin
CPLD_SPI/an485_design_example/quartus/SPI_Master.pof
CPLD_SPI/an485_design_example/quartus/SPI_Master.qpf
CPLD_SPI/an485_design_example/quartus/SPI_Master.qsf
CPLD_SPI/an485_design_example/quartus/SPI_Master.qws
CPLD_SPI/an485_design_example/quartus/SPI_Master.tan.rpt
CPLD_SPI/an485_design_example/quartus/SPI_Master.tan.summary
CPLD_SPI/an485_design_example/quartus/SPI_Master.v
CPLD_SPI/an485_design_example/quartus/SPI_Master_assignment_defaults.qdf
CPLD_SPI/an485_design_example/quartus/db
CPLD_SPI/an485_design_example/quartus/db/prev_cmp_SPI_Master.asm.qmsg
CPLD_SPI/an485_design_example/quartus/db/prev_cmp_SPI_Master.fit.qmsg
CPLD_SPI/an485_design_example/quartus/db/prev_cmp_SPI_Master.map.qmsg
CPLD_SPI/an485_design_example/quartus/db/prev_cmp_SPI_Master.tan.qmsg
CPLD_SPI/an485_design_example/quartus/db/SPI_Master.db_info
CPLD_SPI/an485_design_example/quartus/db/SPI_Master.sld_design_entry.sci
CPLD_SPI/an485_design_example/quartus/db/SPI_Master.eco.cdb
CPLD_SPI/an485_design_example/testbench
CPLD_SPI/an485_design_example/testbench/SPI_Master_test.v