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CPLD_USB
- ：CPLD 可编程技术具有功能集成度高、设计灵活、开发周期短、成本低等特 点。介绍基于ATMEL 公司的CPLD 芯片ATF1508AS 设计的串并转换和高速 USB 及其在高速高精度数据采集系统中的应用-: CPLD programmable technology with a high degree of functional integration, design flexibility, short development cycle, and low cost. ATMEL-b
74595
- 串并转换仿真，内有详细说明和仿真波形，能够成功运行-SERDES simulation
auk_sdsdi
- 用于FPGA设计的代码（Verilog代码），在FPGA设计中的高速串并转换，时钟提取，对齐处理等功能-for FPGA design ,written by Verilog HDL the functions include SERDES , CDR and so on
s2p
- 一个串并转换的Verilog源码，有questasim仿真。-A string and convert the Verilog source code, there are questasim simulation.
serial
- 一个基于单片机串口通信的程序，包含串并转换电路驱程序，驱动光二极管闪动程序， 串口发送和接收程序！-A microcontroller-based serial communication programs, including string and convert the circuit-drive programs, drivers, LED flashing program, serial port to send and receive programs!
434343
- 这是一个用VHDL语言设计的8位串并转换器，立面有点错误自己仿真修改下-This is a design using VHDL language and the 8-bit string converter, elevation changes a little bit wrong, under their own simulation
ser_par
- 24bitAD数据采样进行串并转换，并行输出。另包括24位DA并串转换，串行输出。-24bitAD data sampling and converted to strings, parallel output. Other notable features include 24-bit DA and string conversion, serial output.
ctos
- 利用vhdl完成基于spartan3E开发板的串并转换-Use vhdl complete spartan3E development board based on the string and convert
chu_bing
- 串并转换的一点总结希望对大家有一定的帮助谁有好后点的意见与我联系一下-String and convert the point summed up hope everyone who has a good help to a certain extent after the point of view contact me about
68140323
- vhdl实现了串并转换，和并串转换，可供大家参考学习！-vhdl realized and string conversion, and and the string conversion, for your reference to learn!
chuanbin
- 对信号进行串并转换，使其分成I,Q2路输出信号 -String and convert the signal to make it into I, Q2 output signal
32bitshiftregister
- 32位带锁存移位寄存器,采用verilog HDL语言编写，可用于串并转换-32-bit shift register with latches, using verilog HDL language can be used for string and convert
cbzh
- 串并转换的verilog文件带仿真结果图片的-String and convert the verilog file with simulation results pictures
Para_to_Seril
- 用VHDL实现串并变换的程序，FPGA测试成功，正确变换。-String with VHDL implementation and transformation procedures, FPGA test successfully, the correct transformation.
SERDES
- 基于Verilog的串并转换器的设计与实现，采用两种不同的方案来实现串并和并串转换的功能，并用ISE软件仿真以及chipscope的调试-Verilog-based serial and parallel converter design and implementation of two different programs to achieve the string and and and string conversion functions, and use the ISE softwa
sipo8
- 串入并出源代码，可进行8位数据的串/并转换。其中包括QUARTUS2的完整工程，有正确的仿真波形供参考。-In series and the source code, can be 8-bit data series/parallel conversion. Including QUARTUS2 complete project,and the correct simulation waveform for reference.
sequence_FPGA
- 这个是一个集m序列发生器、序列检测器、并串转换、串并转换等功能，已通过测试。-sequence
cb
- 实现串并转换，非常好用的，已经经过仿真验证的，可以通过。-String and convert to achieve, very easy to use, has been verified by simulation, you can.
11071222426689
- 用vhdl实现1:8串并转换,希望对大家有用。-the vhdl chuan bing zhuan huan
串并转换
- vhdl实现串并转换，其中附有源程序和testbench程序，可以用modelsim仿真