搜索资源列表
multiplier_ip
- 基于IP核的乘法器设计,multiplier_ip中包含完整的工程设计文件,用户可以在Xilinx ISE下运行-Based on IP core of design, multiplier_ip on time-multiplier contain complete engineering documents, users can run Xilinx ISE
mltiply_machine
- verilog语言写的乘法器,每一步经过验证,毫发无损,拿出来与大家共享,在quartus II 上编程,仿真在cyclone 2上!!谢谢!-written multiplier verilog language, every step of the proven, intact, and show to share the quartus II on programming, simulation in cyclone 2 on! ! Thank you!
pipe_mul8
- verilog实现的流水线8位乘法器,效率高,代码简洁经典-verilog implementation of pipelined 8-bit multiplier, efficient, simple and classic code
VHDL乘法器的设计
- 基于VHDL语言的乘法器的详细设计实验报告。
Multipliers
- 各种乘法器,不同算法类型的,适用于不同情况。(Various multipliers, different algorithmic types, are applied to different situations.)
original_code_multiplier
- 16位原码乘法器,附带测试程序,实现两个16位的乘数相乘。(16-bit original code multiplier with test program)
unsigned_array_multiplier
- 4X4位的无符号型阵列乘法器,可以提高乘法的运算速度(4X4 bit unsigned array multiplier, can increase the multiplication of the operation speed)
Multiplier
- fpga门电路实现的8位乘法器, verilog 语言编写,ise平台(implementation of multipler)
mul8
- 用verilog设计了一个两个8位二进制数的乘法器(A multiplier of two 8 bit binary numbers is designed with Verilog)
mux16
- 用verilog写的乘法器,在quartus里可以直接运行,有详细注释(Multiplier written in Verilog, in quartus can run directly, with detailed notes)
mul
- 设计一个简答乘法器,实现计算功能,,,,,,,(Design a simple multiplier)
16bit-multiplier
- 实现verilog16位乘法器,verilog新手(achieve 16-bit multiplier)
booth
- 基于booth算法的16位乘法器,通过减少部分积的运算次数提升速度。(The 16 bit multiplier based on the Booth algorithm improves the speed by reducing the number of arithmetic times of the partial product.)
17
- CSD实现一个乘法器,是一个十一位乘以十七的乘法器,可用于滤波器的相关乘法器设计。(CSD implements a multiplie)
流水线乘法累加器设计
- 调用寄存器LPM,流水线加法器LPM,流水线乘法器LPM等模块实现一个8位流水线乘法累加器。(Call a register LPM, pipelined adder LPM, pipeline multiplier LPM and other modules to achieve a 8 bit pipelined multiplication accumulator.)
16 bit signed number multiplier
- 16位有符号数乘法器,使用Booth编码和华莱士树,提供程序源文件和测试文件(The 16 bit signed multiplier uses Booth encoding and Wallace tree to provide source files and test files.)
mux16
- 基于quartus的FPGA乘法器Verilog程序(FPGA multiplier program based on quartus)
float_mult32x32.v
- verilog 语言写的FPGA内部实现硬件浮点乘法器的源码,两个时钟周期完成一次浮点乘法运算(The FPGA language written in Verilog implements the source of the hardware floating point multiplier, and completes the floating point multiplication operation in two clock cycles.)
multiplication
- 在FPGA里面实现了多位乘法器的功能,并用modelsim进行了仿真,还对该乘法器进行了优化(The function of multi-bit multiplier is realized in the FPGA, and it is simulated with modelsim, and the multiplier is optimized)
fpmul
- Verilog语言编写的单精度浮点数乘法器(The Verilog language of single precision floating point multiplie)