搜索资源列表
mydecoder
- VHDL编写的4*8解交织的代码，自己写的~-VHDL prepared by the 4 * 8 deinterleave code, written in their own ~
cf_interleaver2
- interleaver即交织器，里面包含有C,VHDL,VRILOG HDL三种语言写的交织器, 包括各种各样的组合达六七十种，描写详尽，是一个难得的学习交织器的材料 -interleaver that interleaver, which contains C, VHDL, VRILOG HDL three languages to write the interleaver, including a variety of combinations to depend species,
hanmingjiaozhi
- 通过VHDL实现汉明码，交织码的编码与解码，开发环境Quartus
address_gen
- 卷积交织的地址生成器，通过编译，很好的代码，珍藏-Convolutional Interleaver address generater
CONVOLUTIONAL_INTERLEAVER
- DVB数据交织,交织深度I=12,已得到应用!-DVB data interleaving, interleaving depth I = 12, has been applied!
deinterleave
- CDMA.1X中，解交织的FPGA实现，程序基于VHDL编写，在XILINX开发板实现。-CDMA.1X, the solution of interwoven FPGA implementation, the program prepared based on VHDL, in the XILINX development board to achieve.
jiaozhiqi
- 是Turbo码交织器的VHDL设计与仿真的文献-Is the Turbo Code Interleaver Design and Simulation of VHDL literature
VHD
- RS编码中用到的交织和去交织程序，VHDL描述，交织深度8-nterlace with VHDL，depth is 8
jiaozhijiejiaozhi
- VHDL代码完成行列交织与解交织的功能实现-the realization of interleaver on VHDL language
interlace
- 根据MATLAB中的伪随机交织器产生的交织图案初始化到ROM中，从ROM中读取交织图案对输入数据进行交织。同时也可根据解交织图案进行解交织，同样的算法。-In accordance with MATLAB generated pseudo-random interleaver initialization pattern woven into the ROM, read from the ROM interwoven interwoven pattern of input data. Can a
OFDM_FPGA
- OFDM的FPGA实现 内含卷积编码 交织，频偏检测 完整的OFDM实现代码 -The FPGA contains OFDM convolutional coding to achieve interleaving, OFDM frequency offset detecting the full implementation code
6soft_247MHz_channel
- lte上行信道解交织解复用: RTL: ack_addr_gen.vhd ack地址产生 data_addr_gen.vhd 数据地址产生 de_interl_mux_con_ctrl.vhd 控制单元 de_interl_mux_con_top.vhd 顶层 de_interl_mux_con_tt.vhd 测试平台 de_mux_ram.vhd ram deinterl_pack.vhd 变量定义 delay.vhd 延迟 delayb.vhd 延迟
15Turbo
- urbo码是1993年法国人Berrou提出的一种新型编码方法。它巧妙的将卷积码和随机交织器结合在一起；同时，采用软输出迭代译码来逼近最大似然译码-urbo code is 1993 French Berrou proposed a new encoding method. It is clever to convolutional codes and random interleaver together the same time, the use of soft-output itera
jiaozhiqi
- 模块化程序，实现块交织源程序。VHDL语言。-The modular block intertwined source. VHDL language.
jiaozhi_1024
- 用VHDL语言实现按字节交织，交织深度为4.每组256字节-Block interleaver
jiaozhi_64
- VHDL语言实现按字节块交织，实现每64字节进行一次交织。-The VHDL language byte block interleaving, once every 64 bytes intertwined.
data_interleaver
- OFDM系统的数据交织模块，使用VHDL语言实现，代码本人亲自撰写，如有疑问可讨论之-the data_interleaver function of the OFDM system