搜索资源列表
SHFRT4_1
- 四位串入并出移位寄存器,实现串并转换,已通过时序验证-Four series in and out of shift register, to achieve string and conversion, has passed the timing verification
verilog
- verilog语言例题集锦 包含加法器，乘法器，串并转换器等verilog源代码-Example Collection contains verilog language adder, multiplier, and converters, such as string verilog source code
seri-para
- 串行数据经过串并转换成4位并行数据输出，而后再经过并串转换成串行数据输出，输出与输入相同，只是有延时-After the serial data string and convert it into a 4-bit parallel data output, and then convert the string through and the serial data output, the output and input the same, but delayed
synchronous
- 1：10串并转换，包括同步检测和字对齐功能。-1:10 string and conversion, including the simultaneous detection and word alignment.
FPGA_common_idea
- 本文讨论的四种常用FPGA/CPLD 设计思想与技巧：乒乓操作、串并转换、流水线操作、数据接口同步化，都是FPGA/CPLD 逻辑设计的内在规律的体现，合理地采用这些设计思想能在FPGA/CPLD 设计工作种取得事半功倍的效果。-This article discusses the four commonly used FPGA/CPLD design ideas and techniques: ping-pong operation, strings, and conversion, pipe
elecfans.comMPSK
- 用VHDL实现的基带信号进行MPSK调制 及串并转换-Achieved using VHDL baseband MPSK signal modulation and SERDES
CPLD_USB
- ：CPLD 可编程技术具有功能集成度高、设计灵活、开发周期短、成本低等特 点。介绍基于ATMEL 公司的CPLD 芯片ATF1508AS 设计的串并转换和高速 USB 及其在高速高精度数据采集系统中的应用-: CPLD programmable technology with a high degree of functional integration, design flexibility, short development cycle, and low cost. ATMEL-b
auk_sdsdi
- 用于FPGA设计的代码（Verilog代码），在FPGA设计中的高速串并转换，时钟提取，对齐处理等功能-for FPGA design ,written by Verilog HDL the functions include SERDES , CDR and so on
s2p
- 一个串并转换的Verilog源码，有questasim仿真。-A string and convert the Verilog source code, there are questasim simulation.
signal_output
- 本文件是可以直接使用下载到FPGA里面使用，里面包含时钟分频电路，串并转换和并串转换电路，多通道信号加权的乘加电路等。-The document may download to FPGA chip to complete the clock divider,serial-to-parallel,parallel-to-serial,and multiple-add circuit for multiple channels weight calculation
serial
- 一个基于单片机串口通信的程序，包含串并转换电路驱程序，驱动光二极管闪动程序， 串口发送和接收程序！-A microcontroller-based serial communication programs, including string and convert the circuit-drive programs, drivers, LED flashing program, serial port to send and receive programs!
434343
- 这是一个用VHDL语言设计的8位串并转换器，立面有点错误自己仿真修改下-This is a design using VHDL language and the 8-bit string converter, elevation changes a little bit wrong, under their own simulation
ser_par
- 24bitAD数据采样进行串并转换，并行输出。另包括24位DA并串转换，串行输出。-24bitAD data sampling and converted to strings, parallel output. Other notable features include 24-bit DA and string conversion, serial output.
ctos
- 利用vhdl完成基于spartan3E开发板的串并转换-Use vhdl complete spartan3E development board based on the string and convert
68140323
- vhdl实现了串并转换，和并串转换，可供大家参考学习！-vhdl realized and string conversion, and and the string conversion, for your reference to learn!
chuanbin
- 对信号进行串并转换，使其分成I,Q2路输出信号 -String and convert the signal to make it into I, Q2 output signal
C550
- 包括16C550芯片串并转换功能的初始化、并转串、串转并等等源代码-Including the Initialization,parallel data to serial mode and serial data to parale mode function of 16C550 chip.
32bitshiftregister
- 32位带锁存移位寄存器,采用verilog HDL语言编写，可用于串并转换-32-bit shift register with latches, using verilog HDL language can be used for string and convert
s_p
- 用Verilog HDL语言进行并串转换，并通过Quartus Ⅱ 功能仿真验证-With the Verilog HDL language and string conversion functions through simulation Quartus Ⅱ
sipo8
- 串入并出源代码，可进行8位数据的串/并转换。其中包括QUARTUS2的完整工程，有正确的仿真波形供参考。-In series and the source code, can be 8-bit data series/parallel conversion. Including QUARTUS2 complete project,and the correct simulation waveform for reference.