搜索资源列表
FPGA_Sample
- FPGA的一些入门程序，包括跑马灯、状态机、USB2.0接口、串口等等。可自己看-Some FPGA-entry procedures, including marquees, state machine, USB2.0 interface, serial ports and so on. Can look up
FSM_CPP
- 讲解有限状态机的C++实现，主要用于网络编程和游戏的AI编程，思想很好-To explain the finite state machine in C++, mainly used for network programming and game AI programming, a good idea
ztjt
- 状态机图是系统分析的一种常用工具，它描述了一个对象在其生命期内所经历的各种状态，以及状态之间的转移，发生转移的原因，条件和转移中所执行的活动。-about c
classic-state-machine-C-code
- 4种经典状态机C代码，代码详细，可供学习者参考-Four kinds of classic state machine C code
FSM
- 一个简单的有限状态机(FSM)的例程：检测二进制序列“11001”-A simple FSM routines: testing the binary sequence "11001"
cpu_fsm.tar
- cpu的verilog的不同状态的状态机实现程序编写-write or reset or read or delay of CPU by verilog
Chapter-8
- 练习八利用有限状态机进行时序逻辑的设计322 -• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on
GCD1
- GCD算法的FSMD实现。即利用有限状态机和数据路径-GCD algorithm order which FSMD using finite state machine and data path
gcd2
- GCD算法的FSM+D实现。即利用有限状态机和数据路径分开-GCD algorithm of the FSM + D realize it is using finite state machine and data path separate
ztj
- 各种类型的状态机，单双进程，mealy,moore值得你拥有-failed to translate
jiaotongdeng
- 此程序为另一交通灯程序，由状态机组成，有一开始按钮、一清零按钮。按下开始后，开始一系列的状态循环。已仿真成功。-This program is another traffic light program, the state machine composed of a start button, a Clear button. Press Start, began a series of state cycle. Simulation has been successful.
state_machine
- 基于FPGA的 状态机控制步进机代码，实现步进机的运转-Based on the FPGA state machine control stepper machine code
zhuangtaiji
- 用状态机实现序列检测器的设计，并对其进行仿真和硬件测试。-With the sequence detector state machine design, and its simulation and hardware testing.
alarm_judge
- 基于VHDL语言的闹钟音乐模块。改变状态机中的乐谱可以实现不同音乐-music unit based on VHDL. Changing rhymth in state machine in order to play different music.
I2C_9883_60
- I2C配置程序，通过状态机将数据写入从机，并实现配置-I2C Configuration program, the state machine
EDA-experiments-based-on-VHDL
- 上传的文件包括E有关EDA实验的程序，比如FIFO，秒表，数字钟，七段数码管，状态机检测序列-The files uploaded contain some source code of EDA experiments based on VHDL, such as FIFO, digital clock, stop watch, digital tubes and sequential detector.
EDA
- 彩灯控制系统及状态机程序设计，主要源程序及仿真图、状态图-Lights control system and state machines
machine-design-
- 状态机实现序列检测器的设计，了解一般状态机的设计与应用-State machine to implement sequence detector design, understand the general state machine design and application
Nixie-tube
- 这是一个verilog HDL语言代码，主要利用状态机控制数码管，从0到9循环显示。-This is a verilog HDL language code, the main use state machine control digital tube, from 0 to 9 cyclic display.
traffic_light
- 基于VHDL的交通灯，状态机实现,FPGA参考小程序-VHDL-based traffic lights, the state machine to achieve