搜索资源列表
Phoenix2
- 用VHDL设计一个双进程状态机, 状态0时如果输入“10”则转化为另一状态,否则输出‘1001’; 状态1时如果输入“11”则转化为下一状态,否则输出‘0101’; 状态2市如果输入“01”则转化为下一状态,否则输出‘1100’; 状态3时如果输入“00”则转化为状态0,否则输出'0010'; 复位状态为0-conditional machine
zhuangtaiji
- vhdl状态机程序,经实验验证,没有错误!完美运行,可以用以了解状态机的初步应用!-vhdl state machine program, proved by experiments that there are no errors! Perfect run, can be used to understand the initial application of the state machine!
fengsuyi
- 状态机程序,包含矩阵键盘,模块化程序,针对风速仪的一个简化版的程序。-status program,
Finite-state-machine
- 有限状态机在嵌入式软件中的应用 简述了有限状态及的基本概念和传统理论,提出了利用有限状态机进行程序设计的基本思想。-Finite state machine in the embedded software Finite state and the basic concepts and theories, the basic idea of the finite state machine programming.
State_Machine
- 状态机的VHDL实现,在quartus-ii7.2上测试通过,文件包括米利状态机,摩尔状态机,ADC0809的状态机实现,序列检测器和定时去毛刺的状态机实现。-State machine code in VHDL,successfully tested in quartus-ii7.2,the file contains mealy state machine,moore state machine,ADC 0809 and sequence detector achieved in state
communication-controller
- 该异步通信控制器主要采用状态机设计完成。包括异步发送端和异步接收端。可异步进行信号的收发-The asynchronous communication controller mainly USES the state machine design completed. Including asynchronous the sender and receiver asynchronous. Can signal to send and receive the asynchronous
I8251A
- Verilog 异步串行收发器,收发器的设计,时序状态机的代码编写
The-traffic-light-controller-VHDL
- 基于VHDL的交通灯控制器设计,红灯45秒,黄灯5秒,绿灯40秒,运用状态机原理-The traffic light controller design based on VHDL
SMaRt-v0.6
- BFT-smart是一个能拜占庭容错的状态机复制库,在Java下开发,具有简单性和鲁棒性。我们的主要目的是提供一个代码库,可用于建立可靠的服务,还扩展到创造新的协议。-BFT-SMaRt is a high performance Byzantine fault-tolerant state machine replication library developed in Java with simplicity and robustness as primary requirements. O
schk
- 用状态机实现序列检测器的设计,熟悉用状态机设计各种序列检测器的思路和方法-Sequence detector state machine design, familiar with the ideas and methods of the various sequence detector state machine design
ADCINT
- 用状态机对ADC0809采样控制电路的实现-ADC0809 sampling control circuit using a state machine implementation
Frame-synchronizer-
- 原创,帧同步器的Verilog代码,在FPGA上验证实现过,无误。作为通信系统帧传输的仿真,有限状态机同步态和失步态的切换仿真。-Original Verilog code for frame synchronization, verify the implementation on the FPGA, and correct. Frame transmission as the communication system simulation, finite state machine sync
Project2
- 1、 硬件部分包括AT89C52、LCD1602和4个独立按键 2、 使用定时器0产生10ms的定时中断,作为时钟基准和软件定时器的基准。 3、 系统使用两个软件定时器Tkeyscan和Tdisplay。 Tkeyscan用来独立按键模块的定时扫描,每次扫描结合按键状态机的当前状态判断按键的有效性(消抖)及其时长(长按还是短按)。 Tdisplay用来定时激活LCD1602的显示(200ms一次,可自行修改)。 4、 整个系统在四种状态间流转:DISPL
Traffic-observation-light-Solution1
- c语言教程,自动状态机之交通信号灯的信息处理事例。方法一-c language tutorial, the traffic lights of the automatic state machine information processing examples. Method 2
FPGA_ps2_lcd
- FPGA实现 LCD1602 显示 PS/2 键盘的键值,熟悉并掌握液晶 1602 显示屏的使用方法及PS/2键盘的接口标准,学习利用Verilog-HDL语言编写有限状态机实现较为复杂的设计与应用。-LCD1602 FPGA realizing that the PS/2 keyboard keys, familiar with and master the use of liquid crystal display 1602 method and PS/2 keyboard interfac
state
- verilog 应用状态机设计的序列检测器-verilog ,state machine
par_bak
- 本程序旨在完成 并口 sram 232串口的通信实验 作者亲测可以使用。程序设计到两个时钟及多进程通讯和单进程状态机的基础模块。-This program is designed to complete the parallel port SRAM 232 serial communication experiment of pro-test you can use. Programming to the basic module of the clock and multi-process c
mealy
- mealy型状态机的描写,里面有详细的步骤和源程序-mealy state machine descr iption, there are detailed steps and source code
clock
- 状态机之间的转换,共有8个状态,可以设置时间小时,分钟,显示时间;还可以进行闹钟设置-Conversion between the state machine, a total of eight state can set the time to hours, minutes, display time alarm clock set
lcd1602_test
- 实现1602的驱动,可以显示所需要的内容,驱动程序根据状态机原理写的-1602 drivers can display the content needed, the driver is written according to the principle of a state machine