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yuyincaiji
- 语音采集与回放系统源代码：1.为了使读音数据存储的时间更长，速度更快，选用了256K*16Bit的SRAM；2.为了减少单片机的控制复杂度，使用了FPGA来控制SRAM的读写操作，节约了不少单片机的I/O资源；3.为了以后的高速数据存储，本设计中加入了fifo,其位宽及深度可在程序中自由设置，方便灵活。-Speech acquisition and playback system source code: 1. In order to make pronunciation longer data
SRAM_Proj
- SRAM 读写VERILOG HDL源码-SRAM read and write VERILOG HDL source code
IS61WV51216BLL
- 备注：使用的是VeriLog HDL语言 软件环境xilinx ISE 10.1，硬件：高教仪EXCD-1FPGA电路板。FPGA信号：spartan-3e . 功能编写硬件描述性语言实现FPGA对板上外设SRAM IS61WV51216BLL的读写，通过串口发送到上位机上，使用串口助手显示读取的数据。-Note: Use the VeriLog HDL language software environment xilinx ISE 10.1, hardware: Higher M
PLD
- PLD实验代码，包括格雷码计数器、键盘扫描和LED点阵显示、SRAM读写、LCD12864显示汉字。-PLD experimental code, including the Gray code counter, keyboard scanning and LED dot matrix display, SRAM read and write, LCD12864 display Chinese characters.
zbt_test
- zbt sram测试VHDL程序，实现了FPGA与ZBT SRAM之间的接口控制，在FPGA内能实现对ZBT SRAM读写-vhdl program for ZBT SRAM test
SRAM_rw_test
- C8051F040 SRAM 读写测试程序-C8051F040 SRAM read and write test procedures
sram
- 数据读写进SRAM后送屏显示 很好的参考程序-Read and write data into the SRAM display good reference evacuation procedures
sram
- SRAM的VHDL设计，设计了一个具有4位地址线，8位数据线的SRAM，读写功能独立-SRAM VHDL design, the design of a 4-bit address lines, 8 data lines of SRAM, read and write functions independent
verilogsram
- 基于verilog的读写SRAM控制lED灯的程序-verilog ， SRAM， LED
test-of-62256
- 单片机对sram62256 的读写，sramUT62256CPC-70LL单片机驱动程序-Microcontroller sram62256 read and write, sramUT62256CPC-70LL chip driver
sram-test
- 静态RAM 的读写操作 测试文件，很适合初学者和相关工程人员-SRAM test DOC for engineer
SRAM
- 一个用verilog语言实现的SRAM读写的完整的FPGA工程-A project about sram
SRAM
- 文件中包含了在MDK及IAR两种开发工具下的SRAM读写访问驱动代码，已调试通过。-Contained in the file under the two development tools for MDK and IAR SRAM read and write access to the driver code has been through debugging.
FPGA-SRAM
- FPGA 实验、SRAM 读写实验，达尔EDA 实验室EP2C5 型或EP2C8 型FPGA/SOPC 实验板—dl2c58c_v3-Experimental FPGA, SRAM read and write experimental, Total the EDA lab EP2C5 type or the EP2C8 type FPGA/SOPC experimental board-dl2c58c_v3
sramright
- 控制SRAM的读写； 向SRAM中写入12个数据，这12个数据由助教随机给出； 当按下4×3键盘上的按键时，读出对应的数据，并显示在七段数码管上； SRAM为16位，用16进制表示为4位字符，对应4个七段数码管； -Control SRAM read and write write to the SRAM 12 data, the 12 random data is given by the TA when you press the 4 × 3 keys on the ke
verilogsram
- FPGA Verilog HDL 读写SRAM-SRAM FPGA Verilog HDL to read and write
sram-io
- cycloneII 芯片的4块static ram的读写控制-cycloneII 4 static ram chips read and write control
SRAM
- 使用Verilog语言编写的SRAM读写程序,不用添加IP核,在Xilinx Spartan-6上运行通过,是很好的Verlog程序-SRAM using Verilog language literacy program, do not add the IP core in Xilinx Spartan-6 run through, is a very good program Verlog
sram
- 该实验实现了对SRAM 的每一个地址进行遍历读写操作，然后比对读写前后的数据是否 正确，最后通过一个LED 灯的亮灭进行指示-The experimental realization of the SRAM to traverse each address read and write operations, and then compared before and after the data is read Correct, and finally through an LED fo
SRAM
- 利用程序实现SRAM_读写测试，先进行初始化，读写操作，里面的页操作和bank操作。-Using program SRAM_, speaking, reading and writing tests, first initialized, read and write operations, the inside of the page and bank operation.