搜索资源列表
hdl
- ACTEL串口收发 Verilog语言描述-ACTEL serial port transceiver
hdl
- ACTEL FPGA 1602显示，verilog描述-ACTEL FPGA 1602 show, verilog descr iption
hdl
- ACTEL FPGA 交通灯，Verilog描述-ACTEL FPGA traffic lights, Verilog descr iption
Two_port_RAMa
- Mactel公司的TWO PORT RAM的详细使用指南，通过具体的实例，解释的特别清楚，对于使用actel公司的fpga芯片来说帮助很大！-TWO PORT RAM Mactel' s detailed user guide, through specific examples to explain the particularly clear, for use actel fpga chip company is very helpful!
shift_reg
- actel fpga ap030 regshift示例-actel fpga ap030 regshift
CoreSPI
- 数字电子设计fpga设计的spi接口的ip_core，可以直接用于在fpga设计，支持actel的fpga芯片，支持主从模式，fifo大小可选。-Fpga design of digital electronic design spi interface ip_core, fpga design can be directly used to support actel the fpga chip, support master-slave mode, fifo size options.
RTC
- actel fpga开发板fusion startkit实验例程，包含完整工程文件几verilog HDL 源码-actel fpga development board fusion startkit test routines, including the complete works of several verilog HDL source file
Libero8.3
- 介绍了 Actel FPGA 的集成开发环境 IDE 的使用，从软件的安装和设置，以及 通过一个简单的例子说明如何使用 IDE中集成的第三方软件，如：Synplify、ModelSim等，可以帮助读者快速入门，缩短开发时间。-Actel FPGA introduced the use of IDE integrated development environment, from software installation and setup, as well as through a sim
UART
- actel 公司 Fusion StartKit开发板串口实验，采用veilog 语言编写，易于理解-actel Company Fusion StartKit development board serial experiments using veilog language, easy to understand
AX_Clock_Dithering_AN
- Frequency fine tuning and clock dithering using ACTEL FPGA devices.
Cross_Reference_Guide_rar
- 硬件开发，器件选型，actel的fpga替换文档-Hardware development, device selection, actel the fpga replace the document
D_latch
- actel fpga Verilog D锁存器-actel fpga Verilog D latch
my_RAM
- pdf actel fpga verilog ram读写-pdf actel fpga verilog ram read and write
AES_test
- verilog AES解密 ACTEL FPGA-verilog AES ACTEL FPGA
actel_FPGA_example_source
- actel中的FIFO的使用的示例代码，对于使用actel环境的初学者有一定的帮助。-actel the use of FIFO in the sample code for beginners to use actel environment will certainly help.
AFDX_Solutions_AN
- This application note begins with an overview of AFDX and ARINC 664. Following the overview is an explanation of how engineers could implement an AFDX-compliant interface (ARINC 664, Part 7) using Actel devices and intellectual property. Core10/1
EasyFPGA060_Routine_AESEncrypt
- Actel公司的FPGA实现AES加密的程序及说明文档-Actel' s FPGA implementation of AES encryption procedures and documentation
ExternSRAM
- actel fpga fusion kit操作外部sram程序-actel fpga fusion kit operating procedures for external sram
GateDriver
- actel fpga fusion kit 操作端口-actel fpga fusion kit operating port
usb-blaster
- FPGA的jtag下载线，适用于Actel系列。-FPGA-jtag download cable for Actel series.