搜索资源列表
cpu
- 简易cpu 课程设计 vhdl modelsim-Easy cpu curriculum design vhdl modelsim
20130422-show-cpu-and-memory-message
- 实时显示CPU和内存信息,对于经常编程的人很有用,对像我这种想随时了解CPU及内存情况的也很有用。不用打开任务管理器即可方便直观观察到,随时了解计算机的CPU占用率和已使用内存。 程序功能单一,只显示,而是不占你任何界面,对你操作系统无任何影响,在任务栏右下方不起眼的位置显示,在系统日期左边,字不大,想看的时候看一眼,右键弹出菜单只有一个选项:退出。系统运行占用CPU:0 占用内存:7.8M-Real-time display CPU and memory information, f
CPU
- 东南大学VHDL课程CPU设计 Verilog语言-Southeast University, CPU design Verilog language VHDL course
cpu
- 单片机模拟CPU接口,对其他工作芯片寄存器的读写操作-CPU chip analog interface chip registers to other work read and write operations
single-CPU
- 使用Logisim来创建一个16位单时钟周期CPU,可以执行load,store,加减与或还有转移指令的操作。-Use Logisim to create a 16-bit single-cycle CPU, you can perform load, store, or there is a branch instruction with addition and subtraction operations.
pipelined-CPU
- verilog实现的流水线CPU 通过仿真和下载验证-verilog achieve pipelined CPU verified by simulation and downloads
CPU
- 16位单周期CPU设计 重庆大学 计算机组成原理项目-16 single-cycle CPU design Chongqing University of Computer Composition Principle Project
CPU-Usage
- GDI+绘制适时变化的CPU使用曲线图VB源代码.-GDI+ draw timely changes in CPU usage graph VB source code.
java-Access-to-computer(memory--CPU)
- java获取系统信息(CPU,内存,硬盘,进程)的相关方法和介绍,附上源码,请尽情下载-Java access to information systems (CPU, memory, hard disk, the correlation method and process) is introduced, with source code, please download
multi-CPU
- Verilog开发的能下载到FPGA实验板上运行的多周期CPU-Verilog can be downloaded to the FPGA development board running experiments multi-cycle CPU
take-the-CPU-feature
- e语言模块,取CPU特征字,ec格式加载后使用。E语言模块都是可以自己编写的。-e language module, take the CPU character of the word, ec format after reload. E language modules can all be prepared their own.
CPU-usage
- 这个小程序显示了CPU使用率在至。在zip文件中是一个很好的解释代码(它如何工作)。请投票这个程序-This small program shows you the CPU usage in per cent. In the zip file is a very good explanation for the code (how does it works). Please VOTE this program
cpu-occupancy-rate
- 完美解决CPU占用率的获取问题。 WIN7、XP运行OK。-Perfect solution to the issue of access CPU utilization. WIN7, XP runs OK.
CPU
- 基于FPGA控制的ASIC CPU系统设计,全是用VERILOG代码编写,可以做加减乘除运算 -FPGA-based control ASIC CPU system design, all made with VERILOG code writing, arithmetic operations can be done
cpu
- 动态获取本机CPU运行的占用率,可以用来监控系统性能。-Dynamic access to the machine running CPU occupancy rate, can be used to monitor system performance.
cpu-used
- 一款统计 cpu 使用率的源码 ,和windows自带的资源管理器 ,差不多-A statistical CPU usage of the source code, and a resource manager with windows, almost
CPU
- 这是用VB编写的,能根据CPU磁盘序列号生成注册码程序的一个小程序-According to CPU, disk serial number generate code program
16-CISC-CPU-design
- 16位精简指令集的CPU设计,有完整的步骤和原程序可供学习-16-bit RISC CPU design, complete steps and the original program for learning
CPU
- 它可以按照你设定的刷新率从处理器内核中的数字温度传感器(DTS,Digital ThermalSensor)提取数据,而且可以显示每个内核的温度,准确率非常高,它也提供了检测CPU占用率的功能-它可以按照你设定的刷新率从处理器内核中的数字温度传感器(DTS,Digital ThermalSensor)提取数据,而且可以显示每个内核的温度,准确率非常高,它也提供了检测CPU占用率的功能,
cpu
- 8位实验CPU设计利用设计好的指令系统,编写汇编代码,以便测试所有设计的指令及指令涉及的相关功能。设计好测试用的汇编代码后,然后利用Quartus II软件附带的DebugController,编写汇编编译规则。接着,利用DebugController软件把汇编编译之后的二进制代码置入到所采用的存储器中,并对设计好的8位CPU进行测试。-Eight experiments designed CPU design using the instruction set, write assembly