搜索资源列表
VHDLDPLL
- 比较好的技术文章《基于VHDL的全数字锁相环的设计》有关键部分的源代码。-relatively good technical article, "based on VHDL DPLL the design" a key part of the source code.
dpll0226
- 用一片CPLD实现数字锁相环,用VHDL或V语言.-with a DPLL CPLD, VHDL or V language.
DPLL0227+V+qt6
- 用一片CPLD实现数字锁相环,用VHDL或V语言.-with a DPLL CPLD, VHDL or V language.
pll1218
- 用一片CPLD实现数字锁相环,用VHDL或V语言.-with a DPLL CPLD, VHDL or V language.
changyongmokuai
- 智能全数字锁相环的设计用VHDL语言在CPLD上实现串行通信-DPLL intelligent design using VHDL on the CPLD Serial Communication
200761311574149479
- 介绍了如何使用数字锁相环,如何用VHDL实现数字锁相环-on how to use the DPLL, how to use VHDL DPLL
45370466
- 基于vhdl语言描述的dpll，以及图片-Based on the VHDL language is described dpll, as well as the picture
vhdl3
- 介绍一种基于VHDL 语言的全数字锁相环实现方法， 并用这种方法在FPGA 中实现了全 数字锁相环，作为信号解调的位同步模块。-Introduction of a language based on VHDL implementations of DPLL, and this method is implemented in the FPGA digital phase locked loop, as the signal demodulation of bit synchronizatio
mydesign_DPLL
- 实现了数字锁相环设计，可以用于信号的时钟提取供本地时钟使用-the design introduced a method to use DPLL,we can get the local clock from the signal
sfdppllli
- 简单易懂的可配置dpll的VHDL代码。用于时钟恢复后的相位抖动的的滤波有非常好的效果， 而且能参数化配置pll的级数。 已通过测试。 -Straightforward configuration VHDL code dpll. Very good results for the clock recovery phase jitter filtering, and can be parameterized configuration pll series. Has been tested.
USB1.1-VHDL
- USB PHY RX DPLL This source file may be used and distributed without restriction provided that this copyright statement is not removed from the file and that any derivative work contains the original copyright notice and the associated disclaimer.-US
code
- 本源码是基于VHDL语言环境下的基础实验源码，共分七个部分。分别是：序列检测器、数字密码锁、四位有符号数除法、同步FIFO、DPLL的设计以及Cordic 算法实现。对于VHDL的初学者具有极大的参考价值。-The source is based on experimental basis source VHDL language environment, it is divided into seven sections. They are: the sequence detector, di