搜索资源列表
VHDL-DDS
- 基于FPGA的DDS信号源设计,32位相位累加器,产生可调频率-FPGA-based DDS signal source design, 32-bit phase accumulator to generate tunable frequency
DDS
- FPGA产生DDS,未使用IP核,内含VERILOG程序-FPGA generates DDS, unused IP core, containing VERILOG program
DDS
- 本程序利用FPGA实现了DDS的功能,结合高速DA转换器DAC902可以用作波形发生器-This procedure using FPGA implementation of the DDS functions, combined with high-speed DA converter can be used as waveform generator DAC902
SF-CY3-FPGA
- FPGA开发套件,DDS原理性学习,根本性学习-FPGA Development Kit, DDS learning principles and fundamental learning
DDS
- 基于FPGA和stm32的任意波形发生器,全触控实现。很有用的资料啊,2001年电赛题目-Based on FPGA and stm32 arbitrary waveform generator, full touch implementation. Useful information ah, 2001 electric race title
DDS
- 基于FPGA的DDS详细设计方案(附带详细设计方案及代码)-DDS-based FPGA detailed design (with the detailed design and code)
cycloneiii_3c16_signal
- 基于FPGA,DDS原理的双路正弦波信号发生器,含有与msp430通信模块程序。-Based on FPGA, DDS principle of dual sine wave signal generator, communication modules contain msp430 procedures.
dds
- 利用altera的cyclone FPGA芯片,模拟DDS原理,产生频率可调的正弦波,并使用自带的逻辑分析仪仿真成功-The use altera cyclone FPGA chip, analog DDS principle, have adjustable frequency sine wave, and use the built-in logic analyzer simulation success
DDS
- 第一,DDS模块是一个比较常用的用数字方式实现模拟信号的方法,以前一直只用了频率控制,这一次还通过深入理解用上了相位控制,从这个角度来讲,可以用FPGA小菜一碟的实现频率和相位可控的多通道SPWM波,然后再去外加上RC滤波电路和运放电路就可以实现可控正弦波。 第二,这里的DDS模块还有产生一个可逆计数器的计数使能时钟和方向控制时钟,需要具体说说的是,如果你输出的正弦值是8位的,那么你的计数器的计数范围是在0---255---0,如果你输出的正弦值是9位的,那么你的计数器的计数范围是在0--
DDS
- 一个基于FPGA的DDS,可以实现正弦波的频率控制-An FPGA-based DDS, sine wave frequency control can be achieved
dds(9854)_test(sin_cos)(EP1C6)
- 一些采用FPGA产生信号的一些源代码,对一些初学者有用-some FPGA code
DDS-SU
- 本程序采用了FPGA来控制DDS,采用并行方式,时序配置正确,成功地控制了DDS。可以作为初学者的参考。-DDS can produce all types and frequency and various amplitude modulated signals, but also to ensure the continuous phase, so it is widely used, but there may be doubt as to control for beginners DD
dds
- 一种基于FPGA的任意信号发生器的设计代码-An arbitrary signal generator based on FPGA design code
dds
- 在altera的FPGA上实现直接数字频率合成,即用verilog实现DDS,输出正弦波形,在modelsim软件中仿真通过,已包含所有代码和工程以及二进制流文件。-The realization of direct digital frequency synthesis in the Altera FPGA, which is implemented by Verilog DDS, the output sine wave, through the simulation in Modelsim
dds
- FPGA所需要的DDS源码,可实现波形输出,采用VHDL语言,简单易懂。-FPGA need DDS source waveform output can be achieved using VHDL language, easy to understand.
DDS
- FPGA实现DDS波形发生器,多种信号的产生,-FPGA realization of DDS waveform generator to produce a variety of signals,
DDS
- Verilog HDL实现FPGA的DDS功能,含有实验原理与代码程序-FPGA Verilog HDL realize the DDS function, principles and codes containing experimental procedures
DDS
- 基于fpga的正余弦波形发生器,Verilog代码,测试通过。-Cosine waveform generator fpga based, Verilog code, the test passes.
DDS
- 主要现实FPGA中TLV5618模块,学习将模拟电流信号转化为数字信号,并且显示到数码管,本程序范围0-5V-TLV5618 major reality in the FPGA module, learning the analog current signal into a digital signal, and the digital display, the program range 0-5V
DDS-MY-WORK-1
- FPGA模拟数字信号发生器DDS verilog-FPGA analog and digital signal generator DDS verilog