搜索资源列表
uartfifo
- 基于FPGA的串口发送源代码，通过FIFO能够发送一段字符串。-FPGA-based serial port source code, a string can be sent through the FIFO.
FPGA_UART
- 其中讲到的是经典的VHDL的UART设计实例，而且有很详细的解释和分析，适合针对FPGA串口的开发。-Which is referred to the UART VHDL design of the classic examples, and there are detailed explanation and analysis for the serial port for FPGA development.
zigbee_sensor
- ZigBee无线模块实验.rar；基于FPGA-2C35核心；博创实验箱平台。 在quartusII里面添加uart核，利用串口与主控制机相通信，获取从控制机上传感器的的温度、湿度、光敏电阻、热敏电阻等信息（其中主控制机与从控制机是通过zigbee协议通信） -ZigBee wireless module experiment rar core on the FPGA-2C35 Borch experimental box platform. Add uart nuclear qua
UART
- 语言：verilog语言 功能：通过串口控制模块，实现FPGA与串口 通信。 仿真环境：modelsim 综合环境：quartus -Language: verilog language function: through the serial port control module, FPGA and serial communication. Simulation Environment: modelsim integrated environment: quartu
RS232
- 基于FPGA利用程序实现串口RS232与电脑通信-RS232 serial port to communicate with the computer based on the the FPGA use of program
rec
- 利用fpga实现同步串口，经验证无误，供大家参考-Use FPGA to achieve synchronous serial port, experience, certified, for your reference
async_transmitter
- 该程序为RS232串口通信的VERILOG程序，在FPGA上已通过验证，在测试范围内误码率为0-The program for the RS232 serial port communications VERILOG procedures, the FPGA has been validated in the test range of bit error rate is 0
serial_usb
- fpga实现usb口测试 fpga/altera-usb port test fpga/altera
tiaozhi
- 用NIIOS写串口控制程序，控制FPGA及外部D/A,同时产生函数调制信号-Write serial port control program with NIIOS, control FPGA and the external D/A, while producing function modulated signals
uart_rx
- Tcode is in VERILOG HDL (Hardware descr iption language) code is of UART (universal asynchronous receiver&transmitter) receiver . its objective is to accept serial data from port of computer and allow it to come in a FPGA-Tcode is in VERILOG HDL
DMX512_2_23
- 本系统设计利用FPGA设计了一个接在电脑串口上的一个DMX512协议的转接卡，它可以让你的电脑变成一台超强的电脑灯控制台或者调光台、LED控制器等。通过电脑软件，可以控制电脑灯或者其他DMX512协议的设备，比如LED灯、激光灯、PAR灯、DJ设备等等。 本系统还有体积小巧携带方便等特点，足够一般的娱乐场所、多功能厅、会议厅等场所使用，同时采用电脑进行灯光的控制，也可以提升工程的技术含量，显得更高科技。通过简单更改DMX模块的UART部分，还可以将串口转换usb接口，不过由于手头上的FPGA
UART
- 串口测试程序 基于FPGA的MAX II系列的VHDL源程序端口已经设置好-Serial port test program is based on the MAX II family of FPGA VHDL source port has been set up
CPLD
- FPGA与CPLD之间通过串口通信的程序，波特率为9600。-FPGA and CPLD via the serial port communication program, the baud rate to 9600.
miniuart2
- 用ＶＨＤＬ在CPLD/FPGA上实现与PC机的RS232通信-This UART (Universal Asynchronous Receiver Transmitter) is designed to make an interface between a RS232 line and a wishbone bus, or a microcontroller, or an IP core. It works fine connected to the serial port of a
sim_uart
- uart 收发器 verilog 代码，实现自收发功能 sys clk = 25m, baud 9600 停止位1， 无校验位； 代码实现了串口自收发功能，及把从 PC 收到的内容都发送会 PC, 其他波特率，自行修改代码即可，在 alter 的FPGA 上调试通过； -verilog code uart transceiver to achieve self-transceiver function sys clk = 25m, baud 9600 1 stop bit, no par
FPGA_BUS
- 采用ACTEL的FPGA实现外部并行总线与MCU进行通信，完成I/O扩展与串口扩展功能。-ACTEL FPGA implementation using the external parallel bus to communicate with the MCU to complete the I/O expansion and serial port expansion.
uart_tx
- quartus.exe 环境下经过编辑和方针之后，作为FPGA器件的实验用串口发送数据驱动。-quartus.exe edited and policy environment after the experiment as the FPGA device to send data using serial port driver.
uart_rx
- quartus.exe 环境下经过编辑和仿真之后，作为FPGA器件的实验用串口接收数据驱动。 -quartus.exe edited and policy environment after the experiment as the FPGA device to receive data-driven serial port.
chuankou
- 串口，电脑可接受，可发送；fpga实验主板通过串口线同样可接收发送-Serial port, the computer is acceptable, can be sent fpga board experiments also can be received via the serial line to send
FPGA-imitate-RS232
- FPGA仿RS232通讯接口，因FPGA一般无串口，故可设置用户I/O模仿串口功能-RS232 communication interface FPGA imitation, because usually no serial FPGA, it can set user I/O port features mimic