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tlc3548VHDL.rar
- VHDL实现对TLC3548时序的控制 FPGA控制具有时序简单,速率快等优点,VHDL COUNTER TLC3548
coder_counter
- 增量式光电编码器计数器的FPGA实现程序,verilog3段式FSM,异步加载.-Incremental Optical Encoder counter program FPGA implementation, verilog3 struts FSM, asynchronous load.
gh_timer_8254
- VHDL Source code for 8254 timer/counter
Chapter6-9
- 第六章到第九章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例
timer_0
- 计数器的FPGA控制程序，开发平台为ISE或者quartus-FPGA counter control procedures, development platform for the ISE or Quartus
8253
- With realize based on the FPGA programmable timer counter 8253 designs -With realize based on the FPGA programmable timer counter 8253 designs
counter
- 利用fpga实现秒表。秒表有开始停止，清零的功能-FPGA implementation using a stopwatch. Have begun to stop the stopwatch, Clear function
VHDL
- PWM控制就是产生一定周期，占空比不同的方波信号，当占空比较大时，电机转速较高，否则电机转速较低。当采用FPGA产生PWM波形时，只需FPGA内部资源就可以实现，数字比较器的一端接设定值输出，另一端接线性递增计数器输出。当线性计数器的计数值小于设定值时输出低电平，当计数器大于设定值时输出高电平，这样就可通过改变设定值，产生占空比不同的方波信号，从而达到控制直流电机转速的目的。 直流电机控制电路主要由2部分组成，如图1所示： FPGA中PWM脉宽调制信号产生电路； &
Register
- -- Universal Register -- This design is a universal register which can be used as a straightforward storage register, a bi-directional shift register, an up counter and a down counter. -- The register can be loaded from a set of parallel data in
PPT
- 大学EDA课程的课件以及课后部分习题的程序。包括最基本的加法器、计数器、LED显示以及部分高级VHDL程序。-University of EDA software programs, as well as some after-school exercise procedures. Including the most basic adder, counter, LED display, as well as some high-level VHDL procedures.
up_down_counter
- 32 bit up/down counter with count enable based on altera fpga
counter
- 此代码是一个小的计数器，主要驱动FPGA开发板上的LED灯的亮灭。-This code is a small counter, the main driver FPGA development board bright LED lights eliminate.
counter
- a program for the up down counter with clk setting so that it can be ported directly on to fpga nexsys board
DigitalClock
- 基于FPGA的数字电子钟设计，系统总程序由分频模块、“时分秒”计数器模块、数据选择模块、报时模块、动态扫描显示和译码模块组成。得到一个将“时”、“分”、“秒”显示于人的视觉器官的计时装置。它的计时周期为24小时，显示满刻度为23时59分59秒，另外有校时、校分和整点报时功能，并通过数码管驱动电路显示计时结果。-FPGA-based design of digital electronic clock, the system program by the total frequency modul
clock_divider
- clock divider for fpga in verilog and vhdl it contains counter.vhd clock1.v clock_divider.doc-clock divider for fpga in verilog and vhdl it contains counter.vhd clock1.v clock_divider.doc
Fre_Counter_verilog
- 基于ep3c25的FPGA频率计的简单设计（用verilog HDL），直接打开即可-FPGA frequency counter based on ep3c25 of simple design (using verilog HDL), can directly open the ... ...
counter
- fpga实现的计数器-fpga implementation of the counter。。。。。。。。
10-jinzhi-counter
- 10进制计数器 每计数十次有一个进位，是vhdl编程的基础程序，应用于fpga cpld可编程逻辑器件-Total scores of 10 binary counter has a per carry, is the basis for vhdl programming procedures used in programmable logic devices fpga cpld
15-jinzhi-counter
- 15进制计数器 每计数十五次有一个进位，是vhdl编程的基础程序，应用于fpga cpld可编程逻辑器件-Fifth decimal counter 15 counts each have a carry, is the basis for vhdl programming procedures, programmable logic devices used in fpga cpld
ji-shu-qi
- fpga 本例程为加减法计数器，主要实现的加减法计数的功能-fpga counter the routine for the addition and subtraction, addition and subtraction to achieve the main function of count