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ProgramText
- we will use the Spartan3 XC3S200 FPGA to design a specified counter using the language VHDL.-we will use the cables Spartan3 FPGA design to a specified counter using the VHDL language.
FPGA_AT24C16
- FPGA控制E2ROM的程序，内部使用的是多频计数器完成，简单易用-FPGA control E2ROM program, which uses multi-frequency counter is complete, easy to use
ADC_Fre_counter_LED_keyboard
- FPGA tlc082０采样控制 高精度测频 ＬＥＤ键盘显示 ＶＨＤｌ 调试与ＥＰ１Ｃ３-FPGA vhdl ADC LED keyboard frequency counter test
pinglvji
- 做的等精度频率计，采用等精度测量原理，即利用双计数器“相关计数”和“硬件同步分频”实现高低频率的等精度的测量。用FPGA实现频率测量、周期测量、时间间隔测量、相位测量及脉冲宽度的测量。所有的测量功能都由VHDL语言编程实现。-I do other precision frequency meter, use and other precision measuring principle, namely the use of dual-counter " related counts&qu
RISC-CPU
- 用FPGA实现一个简易的CPU，采用精简指令集结构，每一条指令有16bit，高三位为指令操作数，后13位为地址，该CPU能实现8种指令操作，分别有HLT（空一个中期）ADD（相加操作）SKZ（为零跳过）AND（相与操作）XOR（异或操作）LDA（读数据）STO（写数据）JMP（无条件跳转指令）。cpu包括8个部件，分别为时钟发生器、指令寄存器、累加器、算术逻辑单元、数据控制器、状态控制器、程序计数器、地址多路器，各个部件之间的相互操作关系由状态控制器来控制，程序指令存放在初始rom中，本例程存放
sevensegment
- FPGA-Seven segment and counter
EP1C3_12_3_VGA
- 基于FPGA的VGA彩条显示程序，共开发VGA的朋友参考。没有采用DA，因此只有8中颜色（输出直接连到VGA的RGB）。其中行、场同步部分用计数器完成。程序用VHDL编写。-FPGA-based VGA color display, with a total development of the reference VGA friends. Did not use DA, only 8 colors (directly connected to the VGA output of the RGB
Count
- 基于FPGA图形方法的同步模231计数器（设秒脉冲已给） -Graphical method based on the synchronous FPGA module 231 counter (pulse has been set up to)
60jishuqi (2)
- 这是一个可以记到60的计数器，可用于数字钟层次化设计。(This is a counter that can be recorded to 60, and can be used for the hierarchical design of digital clock.)
led
- 利用计数器设计延时函数，通过四个led灯的闪烁，可以直观观察延时时长，fpga器件cyclone iv LCMXO2-1200HC-4TG144CR1,在demo板上作简路图(Using the counter to design the delay function, through the flashing of four LED lights, we can observe the delay time directly, FPGA device cyclone IV LCMXO2-12
gray_counter
- 格雷码计数器实质包含了三个部分 格雷码转二进制、加法器、二进制转格雷码。通过quartus II 自带的Modlesim仿真验证了 能够实现二进制和格雷码之间的转换(Gray counter essence contains three parts, gray code to binary adder, binary gray code conversion. Modlesim simulation by quartus with II verified to achieve the conve
count
- 含异步清零和同步使能的计数器的设计，可以实现计数，异步清零，同步使能等功能(The design of a counter with asynchronous zero and synchronization enables counting, asynchronous zero, synchronization and other functions)
可逆计数器VHDL描述
- 在开发板FPGA：Spartan-3E 系列，型号：XC3S500E，封装：FGT320，速度-4，利用Xilinx ISE软件，利用VHDL软件编写可逆计数器，包含实验说明以及代码实现VHDL.doc文件,UCF管脚绑定文件(In the FPGA:Spartan-3E development board series, XC3S500E, package: FGT320, speed -4, using Xilinx ISE software, written in a reversible
Up_Down_Counter v1.0
- FPGA Up/Down couner Module
counter
- 基于FPGA平台的，计数器的简单实现过程(Code based on FPGA, a realization of VHDL/counter)
黑金Altera开发板Verilog实例教程
- 控制开发板上的4个LED灯，计数器记到4秒清零，控制LED灯依次亮(Controlling the four leds on the development board, the counter down to the 4 seconds reset, the control the LED light in turn)
three
- .实十位加法计数器程序，要求从0-9进行计数2验设计(The ten bit adder counter program requires 0-9 to count from 2.experimental design)
cntCode
- 通用计数器程序，便于初学者掌握verilog HDL语言的进行计数器设计原则(General counter program is easy for beginners to master the counter design principles of Verilog HDL language.)
密码锁
- 程序通过采集输入信息，与FPGA的存储值进行比较，如果密码正确，则开锁电路打开；如果密码错误，锁不打开，并且计数器进行+1操作；累计3次输入密码错误，给警报一个高电平，让其报警。(By collecting input information, the program compares with the storage value of FPGA. If the password is correct, the unlocked circuit opens; if the password is
模24计数器
- 模24计数器的Quartus II文本输入设计及其test bench(Quartus II text input design and test bench of modulo 24 counter)