搜索资源列表
johnson
- JOHNSON计数器，8bit,在FPGA板子上简单的实现，给大家作为练习-JOHNSON counter
Counter_VhdlCode
- it is a simple counter written in vhdl , can be simulated using model sim worked on xillinx for fpga.
Exp1-Led
- 本次实验使用 Xilinx FPGA的开发工具 ISE6.x，新建一个工程，并进行综合、布局布线、 下载配置。 这里建立的工程是使用 Create-SOPCMB上的发光二极管显示一个八位二进制计数器， 发光二极管亮表示该位为 0。 -Experimental use of the Xilinx FPGA development tools ISE6.x, create a new project, and comprehensive, the layout of wiring, d
clock10
- 篮球24秒计数器。用Verilog语言编写，在maxplus2中编译运行。适用于大部分FPGA开发板，但必须更改引脚分配。-24 seconds counter basketball. Verilog language used in compiling maxplus2 run. Applicable to most FPGA development board, but must change the pin assignment.
EDA
- 基于MAX PLUS 2 FPGA 依据状态机结构的10禁止计数器 内附其仿真图-MAX PLUS 2 FPGA based state machine based on the structure of the 10 counter containing the prohibition of the simulation map
FPGA_Counter
- 利用FPGA设计的可以自适应的频率计，里面有详细的文档介绍。-FPGA designs can use adaptive frequency counter, which document describes in detail.
contadorbcd
- BCD Counter with FPGA for practice
cnt4_10
- 用VHDL在FPGA开发板上实现4位十进制计数器 -Use VHDL to achieve 4-bit decimal counter
Frequency_Counter
- 基于ep3c25的FPGA频率计的简单设计（用VHDL编写），直接打开即可-FPGA frequency counter based on ep3c25 of simple design (using VHDL written), directly open a can ... ...
dianzizhong
- 利用FPGA实现电子钟，包括计数器控制器。-Using FPGA to achieve clock, including the counter controller.
chap8_CntStep
- FPGA学习资料-VHDL语言实现的计数器-FPGA-VHDL language learning materials counter
success
- 各种FPGA初级入门程序（已调试通过），包括计数器、流水灯、7段数码管显示以及PS2键盘接口驱动，采用VHDL语言编写，适合初学者参考-Various FPGA primary entry procedures (already debugged), including the counter, water light, 7 segment LED display and PS2 keyboard interface driver, using VHDL language, suitable f
plj
- 此程序为fpga的频率计vhdl程序,功能是可以检测到输入信号的频率并且通过八位数码管显示-This procedure is the frequency counter vhdl fpga program function is to detect the frequency of the input signal and the digital display by eight
A_VHDL_Timer
- 8254计数器fpga实现vhdl语言英文说明文档-8254 counter vhdl fpga implementation language English documentation
counter100
- VHDL语言 FPGA 一百进制计数器 元件例化方法-VHDL, FPGA hundred cases of binary counter element method
jishuqi
- 计步器程序 使用vhdl描述 实现实时的计步功能 用fpga实现已通过-step counter Pedometer programs use VHDL achieve real-time project described in step function already through fpga realizing
numarator
- counter source code in vhdl, implemented on fpga
Clk50M_div_1HZ
- Clk50M_div_1HZ，调试已通过，采用计数器分频 此实验采用计数器，将板载的50MHz时钟源分频为1Hz，分频的结果以LED灯的形式显示。下载电路至FPGA后，会发现LED0会以1Hz的频率闪动。-Clk50M_div_1HZ, using counter this study, frequency counter, onboard 50MHz clock frequency of 1Hz, frequency results in the form of LED lights di
ftctrl
- 基于FPGA实现的32位计数器，可控制计数位宽。-FPGA-based implementation of the 32-bit counter, can control the counting bits wide.
Ring4
- 用verilog代码编写的环形计数器的FPGA工程。-Verilog code written with the ring counter.