搜索资源列表
mc8051
- 可在FPGA上运行的8051 IP core,是学习FPGA及SPOC的好资料。
lcd_com1
- 青云开发的LCD模块LCM240128ZK3用于ALTERA的FPGA,自己写的AVALON总线IP核,供大家参考
xd_lcd_comp
- 一款240*128的LCD模块在ALTERA FPGA NIOS中的应用,自己写的AVALON总线IP,包括所有源码,可轻松用于NIOS中,供大家参考
mc8051_design
- MC8051 IP CoreOregano Systems 8-bit Microcontroller IP-Core此公司提供的8051 core很容易在FPGA 上用同时也是学习VHDL的一份不错的进阶实例-MC8051 IP CoreOregano Systems 8-bit Microcontroller IP-Core company for the 8051 core very easy to use in FPGA VHDL is also studying a good exam
uart_verilog
- 包含UART口的VERILOG源程序,该程序在FPGA上验证通过,可作为芯片设计,或FPGA设计的一个完整IP核,硬件设计的兄弟们可参考一下。-include UART port of VERILOG source, the program tested in FPGA, as chip design, or FPGA design of a complete IP cores, hardware design brothers can make reference.
Quartus+II+++ModelSim+SE+++后仿真+++库文件.rar
- Mentor公司的ModelSim是业界最优秀的HDL语言仿真软件,它能提供友好的仿真环境,是业界唯一的单内核支持VHDL和Verilog混合仿真的仿真器。它采用直接优化的编译技术、Tcl/Tk技术、和单一内核仿真技术,编译仿真速度快,编译的代码与平台无关,便于保护IP核,个性化的图形界面和用户接口,为用户加快调错提供强有力的手段,是FPGA/ASIC设计的首选仿真软件。
静态存储器
- 在FPGA设计IP核中,很有用
USB_1.1IP核
- 这是USB的一个机遇FPGA的IP核设计。欢迎大家使用
wishbone_VHDL.rar
- wishbone总线的VHDL源代码 wishbone适用于与FPGA中IP核的高速通信,其接口简单,速度快 成为ip通信的主流,Wishbone Bus VHDL source code Wishbone applicable to IP core in FPGA high-speed communications, and its easy interface, fast becoming the mainstream of ip communications
SATA_Verification_IP-SystemVerilog
- SATA Verification IP - SystemVerilog,是使用FPGA做的sata接口部分,是一篇文档-SATA Verification IP- SystemVerilog, is to use FPGA to do sata interface part, is a document
ram_fifo_ram
- 程序实现了在FPGA内部开辟RAM+FIFO+RAM的IP核进行数据之间的调试。方便需要用到的童鞋进行参考。已通过modelsim调试-Implemented within the FPGA program to open up RAM+ FIFO+ RAM for data between the IP core debugging. Need to use the shoes for easy reference. Has passed debug modelsim
DDR-SDRAM_IP_core
- DDR-SDRAM接口模块verilog源代码,可用作IP核使用,已在FPGA上验证-DDR-SDRAM interface module verilog source code, can be used as IP cores to use, proven
hardh264
- 一个硬件H264编码的VHDL源码,用于FPGA开发,适合IP摄像头等视频设备输出数据的编码。用Xilinx工具测试过,但代码不只是用于Xilinx。-A hardware h264 video encoder written in VHDL suited to IP cameras and megapixel cameras. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools
bridge
- FPGA和A/D转换芯片ad7862的IP,可实现4路数据的采样和读取。 用verilog实现的-FPGA and the A/D conversion chip ad7862' s IP, can achieve 4-way data sampling and reading. Achieved with verilog
IPcore
- FPGA 的各种 ip core 供大家参考-FPGA various ip core for your reference
DM9000Aethnet
- 国内重点大学使用最广泛的FPGA开发板-DE2板中经常使用的ip核——DM9000A-University of the domestic focus of the most widely used FPGA development board-DE2 board frequently used ip core- DM9000A
CANbus
- 主要是说明can总线协议使用fpga的ip核实现,供使用can总线的人使用-Mainly states can use the FPGA bus protocol of the ip nuclear realized, for people who use the bus can use
xapp529_6_2
- 一些有用的IP核,本人也是刚涉及FPGA到开发,特别希望前辈们能够共享一些关于图像处理方面的IP核-Some useful IP core, and I was just involved in FPGA to development, particularly the older generation to share some information about aspects of image processing IP core