搜索资源列表
tft35inch_2C8_test
- 基于FPGA的ip核lcd控制器 320240分辨率-ip nuclear lcd controller FPGA-based resolution of 320,240
mcu51
- 基于IP核的51mcuFPGA程序，有顶层文件图，可以直接运行，有助于对mcu的工作原理和FPGA的理解-IP core based on the 51mcuFPGA program, there are top-level file map, can be directly run, contribute to the working principle of the MCU and FPGA understanding
ar32713_xlt202a_v5_gmii
- Code ip generator for fpga altera
AHB2APB_Bridge_example_M7
- Cortex-M3+FPGA AHB2APB桥接设计范例, 核心IP不可读，可用。可以综合，测试。-Cortex-M3+ FPGA AHB2APB_Bridge_example， IP core not readable。
ddr
- ddr2控制器设计,适用于xilinx fpga,内含IP软核 -ddr2 controller design for xilinx fpga, embedded IP soft core
axi-timer
- 这是Xilinx AXI定时器的说明手册，对于进行FPGA开发的工程师有参考价值 -The LogiCORE IP AXI Timer/Counter is a 32/ 64-bit timer module that interfaces to the AXI4-Lite interface.
SATA_IP_FPGA
- SATA协议简要分析及其FPGA实现说明- SATA1.0 IP based on Fpga
gtx_interface_ip
- 高速串行设计FPGA-GTX IP设置生成，可动态配置速率2.4Gbps，1.2Gbps，0.6Gbps，自适应链接-High-speed serial design FPGA-GTX IP settings generated dynamically configurable rate of 2.4Gbps, 1.2Gbps, 0.6Gbps, adaptive link
gtx_drp
- 高速串行设计FPGA-GTX IP设置生成drp模块，可动态配置速率2.4Gbps，1.2Gbps，0.6Gbps，自适应链接-High-speed serial design FPGA-GTX IP setting generation drp module, dynamically configurable rate 2.4Gbps, 1.2Gbps, 0.6Gbps, adaptive link
ddr_controller
- 完整的DDR控制器设计，包含代码、仿真环境、FPGA综合网表等-full DDR controller ip,include rtl code,simulation environment and testbench, fpga synthesis netlist,etc.
udpip
- 赛灵思XILINX FPGA verilog写的UDP/IP协议，可用。-I am prepared to use verilog UDP protocol, the test is available.
viterbi_soft
- 维特比译码器，调用IP核，软判决输入，开发平台Xilinx Spartan-6系列FPGA-viterbi decoder, using IP core resource, soft decision input,develop platform is Xilinx Spartan-6 series FPGA
PCIE_14_Complete
- FPGA PCIE的IP核控制，可以用modelsim直接仿真，观察信号。-IP core for PCIE of FPGA,able to simulate with modelsim and check the signal
IIC
- FPGA I2C的IP核控制，可以用modelsim直接仿真，观察信号。-IP core for I2C of FPGA,able to simulate with modelsim and check the signal
axi_jesd204b
- ADI JESD204接口的ADC与Xilinx FPGA接口IP，包含Verilog和VHDL源代码，AXI总线接口，ADC串行控制接口-ADI IP for interfacing JESD204 ADC to Xilinx FPGA, include Verilog/VHDL source code, AXI interface and serial config interface
uart_test
- altra fpga nios 开发uart工程-UART IP and test on nios
ug479_7Series_DSP48E1
- 该文档详细介绍了XILINX FPGA内部重要的IP核DSP48E的应用方法，官方手册，准确无误-This document describes in detail the XILINX FPGA internal IP core DSP48E application method, the official manual, accurate
ROM
- 使用verilog语言实现对altera下cycloneII系列FPGA的片上ROM的创建，读写，调用IP核-Use verilog language to achieve altera under the cycloneII series FPGA on-chip ROM to create, read and write, call IP core
Version1_6
- 基于VHDL硬件语言描述的mc8051的IP核，适用于将8051IP核移植到FPGA开发板上的实验，极大的减轻了初学者的工作量- U57FA u4E8EVHDL u786C u4EF6 u8BED u8A0 u63CF u8FF0 u7684mc8051 u7684IP u6838 uFF0C u9002 u7528 u4E8E u5C068051IP u6838 u79FB u690D u5230FPGA u5F00 u53D1 u677F u4
UART_FIFO
- FPGA，串口调试程序，接收模块，含FIFO IP核-FPGA uFF0C u4E32 u53E3 u8C03 u8BD5 u7A0B u5E8F uFF0C u63A5 u6536 u6A21 u5757 uFF0C u542BFIFO IP u6838