搜索资源列表
FFT_IP
- Xilinx FPGA 的IP核，实现FFT功能的-Xilinx FPGA IP core, FFT function
PS2-IP-CORE-VHDL
- 一个PS2 IP CORE(VHDL) for FPGA
designgamebasedonFPGA
- Run Pac-man Game Based on 8086/8088 FPGA IP Core
XILINX全系列产品选型速查指南
- 包括XILINX的FPGA、CPLD、IP、工具、开发板等
uart8.zip
- 使用Libero提供的异步通信IP核实现UART通信，并附带仿真程序。UART设置为1位开始位，8位数据位，1位停止位，无校验。且UART发送自带2级FIFO缓冲，占用FPGA面积很小。,Libero provided the use of asynchronous communication IP core implementation UART communications, and incidental simulation program. UART is set to 1 to sta
C8051IP.rar
- FPGA应用，51单片机的IP核，在FPGA中嵌入单片机的源代码,FPGA applications, 51 MCU IP core, single-chip embedded in the FPGA source code
FSK
- 利用FPGA内的IP核来实现FSK，Using FPGA to realize the IP core FSK。-Using FPGA to realize the IP core FSK,
can.rar
- can IP CORE .VERY GOOD AS A STUDY FILE,can IP CORE. VERY GOOD AS A STUDY FILE
DDS.rar
- Quartus中实现的DDS 使用的是altera提供的IP core,DDS achieved Quartus using IP core provided by altera
PCI-IPcoreor1k[1]
- PCI的ip core，VHDL代码，希望对大家有帮助-PCI-ip core, VHDL code, we hope to help
FFT_verilog
- verilog实现的FFT变换，经硬件测试其功能与Altera的FFT IP核相近-verilog implementation FFT transform, through hardware, test its functionality with Altera' s FFT IP core similar to
ethernet
- 以太网MAC层IP核设计Veriolg代码，包括TESTBECH平台和设计文档-Ethernet MAC layer IP core design Veriolg code, including TESTBECH platform and design documents
HDLC
- verilog HDL语言编写的HDLC协议的IP核，包括通讯控制及CRC。-written in verilog HDL HDLC protocol IP core, including communications control and CRC.
USB2.0IP(RTL)
- USB2.0 IP核,ASIC,FPGA可用,Verilog HDL源代码-USB2.0 IP,Verilog HDL
Verilog_UDP
- 辛辛苦苦找到的UDP的资料，在verilog中UDP指的是用户定义的原语。比如说大家有时候会见到“primitive...table...endtable...endendprimitive”这样的代码段，在书上只能找到大概的解释。到网上查的话又老是跟TCP/IP的UDP冲突。所以特地搜集到了这个东西，希望能帮助大家解决“用户原语”相关的问题。-UDP hard to find the information in verilog in the UDP refers to the user-de
ARMcore
- 基于FPGA的ARM IP核！该软核VHDL源码全部开放-FPGA-based ARM IP core! The soft core VHDL source code are all open
SPI
- 经典spi IP 核心 FPGA是实现有说明文档-spi IP based on fpga
NAND_Flash_Controller
- FPGA实现的NandFlash控制器（带ECC）文档+源代码。-FPGA implementation NandFlash controller (with ECC) document+ source code.
10100MIP
- 以太网10100M IP核Verilog源码(可综合)\以太网10-100M IP核Verilog源码，可综合-10100M IP Ethernet core Verilog source code (which can be integrated) \ 10-100M IP Ethernet core Verilog source code can be integrated
ipman
- IP包监听程序 -IP packet sniffer