搜索资源列表
hdl-2016_r2
- AD9361 IP核，Windows版本，Vivado2016.2(AD9361 IP core, used on Windows, Vivado2016.2)
spram
- verilog编写的spram，包含顶层模块，控制模块和spram本体，其中spram为Altera提供的ip核，已在quartus 16上运行通过(Verilog written in spram, including the top-level module, control module and spram ontology, where spram is the IP kernel provided by Altera, has been running on quartus 16)
基于FPGA和IP核的FIR低通滤波器
- 用verilog语言实现数字电路低通滤波器(Implementation of digital circuit low-pass filter using Verilog language)
gtwizard_0_stub
- GTX IP 核内部模块，数据收发功能(GTX IP kernel internal module, data transceiver function)
Digital_Tube_Core
- 以ip核的形式来控制数码管显示，减少cpu资源开支。(Digital_Tube_Core/Digital_Tube ip)
Sdram
- 在vivado中调用SDRAM的IP核，并通过数据的读入，读出，验证IP核的使用，文件中有仿真结果时序图。(In the vivado call SDRAM IP core, and read through the data, read, verify the use of IP kernel, the file has simulation results sequence diagram.)
基于AvalonST接口帧读取IP核的设计和应用
- 区别于altera官方的frame reader，完全自定义设计(Different from the official frame reader of Altera, fully custom design)
06_pll_test
- 锁相环IP核的使用，包括详细的配置，适合学习使用；(The use of PLL IP core, including detailed configuration, suitable for learning to use;)
10_rom_test
- rom ip核的配置，以及测试文件，适合初学者使用。(ROM IP core configuration, as well as test files, suitable for beginners to use.)
parallel_norflash_test
- ISE工程，并行nor flash的读、写、擦出，其中有个调用FIFO16-16的IP核，已经在工程中(ISE engineering, parallel nor FLASH read, write, erase, where there is a call FIFO16-16 IP core, has been in the project)
新建压缩(zipped)文件夹
- 讲述ISe软件的使用方式及一些IP核的原理内容(The use of ISe software and the principles of some IP cores)
嵌入式
- 功能 多路外部信号选通输入到LED显示 读取当前LED显示状态 PB or SW 通过标志寄存器配置(function Multiple external signals are selected to be input to LED display Read the current LED display status PB or SW Flag register configuration)
PWM_last
- 在quartus中采用制作软IP核实现PWM波控制LED灯的显示(Using the soft IP in quartus to verify the display of the current PWM wave control LED lamp)
Module基础全集
- 如题，各种veirlog 基础代码大全，虽功能不及ip核，但却可以学习到很多(For example, all kinds of veirlog base code, though not as functional as IP core, can learn a lot)
microblaze_GPIO
- 基于xilinx 的软核microblaze的GPIO IP核程序(GPIO IPcore program for soft core MicroBlaze based on Xilinx)
uart_latest.tar
- UART的VHDL建模代码，是一个标准的IP核(UART's VHDL modeling code is a standard IP core)
modelsim se 10.1a crack
- Mentor公司的ModelSim是业界最优秀的HDL语言仿真软件，它能提供友好的仿真环境，是业界唯一的单内核支持VHDL和Verilog混合仿真的仿真器。它采用直接优化的编译技术、Tcl/Tk技术、和单一内核仿真技术，编译仿真速度快，编译的代码与平台无关，便于保护IP核，个性化的图形界面和用户接口，为用户加快调错提供强有力的手段，是FPGA/ASIC设计的首选仿真软件。(Mentor's ModelSim, the industry's best HDL language simulation
10_rom_test
- 讲解赛灵思Spartant_6系列FPGA的ROM IP核的调试过程，供大家参考学习(Explain Xilinx Spartant_6 Series FPGA ROM IP core debugging process, for your reference learning)
rtl
- 基于S10新品的2x2矩阵乘模块，附带双精度的乘法，除法ip核(2x2 matrix multiplication module based on S10 new product, with double precision multiplication, division IP kernel)
eetop.cn_kc705
- Xilinx PCIE IP核的应用例程，带DMA，有V6和KC705的应用(Xilinx PCIE IP DMA example)