搜索资源列表
6678_pci_duplex
- PCI9656 的控制,ISE 12.2,verilog编写,slave模式-PCI9656,verilog,ISE 12.2,using verilog,SLAVE mode
music
- 利用FPGA模拟弹钢琴的Verilog代码。在Xilinx ISE 14.3 编译通过-Using FPGA Verilog code simulation play the piano. Compiled by Xilinx ISE 14.3
EMAC6
- verilog实现的FPGA三态以太网链路层通信代码,里面有状态机,并按各个模块的功能分了文件夹,还有说明文档,自定义帧的产生和接收,开发环境为Xilinx ISE,测试无误。-verilog realization FPGA Tri-Mode Ethernet link layer communication code, which the state machine, according to the function of each module sub folder, as well a
UART
- 基于ISE 用verilog编写的uart串口通信源码-Based on the ISE written in verilog uart serial communication source code
DigitalWatch
- 用verilog数字钟,并且在ise上验证,可以显示分秒,并且可以对分和秒进行调整-Verilog digital clock, and verified in ise, can display every minute, and you can adjust the minutes and seconds
zhongzhilvbo
- xilinx ise 与modesim联合验证中值滤波 含verilog源程序和整个工程文件-the xilinx ise modesim median filter containing joint verification verilog source, and the entire project file
fpga-fir
- xlinx fpga 利用verilog语言实现fir滤波器功能,完整ise工程文件直接可以使用-xlinx fpga verilog language the fir filter function, complete ise project file can be used directly
CooperativeCommunication
- 1. 研究空时分组码的编译码原理及算法; 2. 研究了几种不同的协作分集系统模型和协作分集协议; 3. 将空时分组码编译码器与协同通信用硬件描述语言Verilog实现,并在ISE集成环境中综合仿真,结果正确后下载到FPGA电路板上; 4. 用示波器观察输出数据是否正确,验证空时分组码协同通信的性能。 -1. Decoding Principles of space-time block codes and algorithms 2. Study several differen
AXI_MIG
- ISE生成的AXI接口的MIG,内存控制器,语言:verilog-ISE generated the AXI interface MIG, memory controller, language: verilog
I2C-bus-based-on-FPGA
- 基于FPGA设计I2C总线,使用Verilog语言,ISE环境,含有仿真结果-I2C bus based on FPGA design using Verilog language, ISE environment containing simulation results
LED_TEST
- Verilog的LED闪烁程序,xilinx ISE开发环境-Verilog LED flashes, Xilinx ISE development environment
ram2114
- 本程序是利用ise平台设计出的ram2114的Verilog源代码,通过上机运行检测。-This procedure is to use the platform to design a ram2114 ise of Verilog source code, the test is run through the machine.
spi
- spi协议 用verilog 编写 可以在xilinx fpga板子上 ise软件-spi protocol written in verilog in xilinx fpga board ise software
my_bayer2rgb
- 摄像头Bayer 转rgb信号 用verilog 编写 在xilinx fpga 软件下 ise 综合 编译-Bayer turn the camera rgb signal in xilinx fpga verilog prepared under ise integrated compiler software
I2C
- iic协议 用verilog hdl语言,可以在xilinx ise软件 编译 综合-iic agreement verilog hdl language can be compiled in xilinx ise software integrated
juanji_3_3
- 自己写的3*3的高斯卷积模板,用Verilog在ISE上写的-Write your own 3x3 Gaussian convolution mask, using Verilog write on the ISE
CRC16_8
- 利用ISE软件采用Verilog HDL语言编写CRC码,每时钟处理8bit数据,在输入序列后最终加上16位校验码。-Using Verilog HDL language CRC code, 8bit data processing per clock, after the final of the input sequence plus 16 checksum.
a
- 用verilog实现除法器,调用了ip核,不仅有源代码,还有测试程序的时序编写-verilog ise divider
multi_cpu
- 用xilinx ISE 14.3开发的多周期CPU系统,开发语言为verilog HDL.仿真调试与实际测试均已通过-Using xilinx ISE 14.3 development of multi-cycle CPU system, development language for verilog HDL. Simulation debugging and practical tests have passed
Watch_Game_0729
- 基于xilinx virtex5的猜数游戏+LCD显示设计,包含完整的ISE工程文件,代码全部用verilog编写,有说明文档。-Based on xilinx virtex5, the guessing game plus LCD display design, including complete ISE project file, all code written in verilog, documents.