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lab2
- 熟悉XUPV2P实验开发平台。熟悉掌握Verilog HDL语言并能用其建立基本 的逻辑部件在Xilinx ISE平台进行输入、编辑、调试、仿真-Familiar XUPV2P experimental development platform. Familiar with Verilog HDL language and be able to establish its basic logical components in Xilinx ISE platform for entering
vga_stripes_top
- VGA彩条显示,分辨率800*600,使用Verilog显示间隔可设置的红绿条纹,使用工具为xlinx ise.-VGA color display with a resolution of 800* 600, the use of red and green stripes Verilog display interval can be set using tools xlinx ise.
cpu_design
- FPGA MIPS架构CPU，五段流水线功能，ISE开发，verilog语言，可综合，模拟结果正确，内含设计报告-FPGA MIPS CPU, simple five-stage pipeline function, developed by ISE, using verilog language
ISEadder
- 利用Verilog语言，基于ISE，设计加法器-ISE adder
UART
- Verilog HDL编写的串口程序实例，很详细好用的参考代码。针对Xilinx FPGA开发板，在Xilinx ISE编译调试成功，串口开发的经典例程。-Verilog HDL serial program written examples, very good reference code in detail. In view of the Xilinx FPGA development board, in Xilinx ISE compiler debugging success, a s
20140825
- FPGA设计在设计过程中使用ISE软件自带的IP核时，消耗资源太大的时候，需要自己编写滤波器的源代码，这里给出我们常用的串行FIR核的verilog语言代码设计文件，并通过作者时序仿真验证，并用于实际的项目中。-The FPGA design in the design process of ISE software used to own the IP core, consume resources is too big, need to write your own source code
FIR
- FPGA设计在设计过程中使用ISE软件自带的IP核时，消耗资源太大的时候，需要自己编写滤波器的源代码，这里给出我们常用的串行FIR核的verilog语言代码设计文件，并通过作者时序仿真验证，并用于实际的项目中。-The FPGA design in the design process of ISE software used to own the IP core, consume resources is too big, need to write your own source code
clk_gen
- this is a clock generator program by using concurrent language verilog hdl with xilinx ise.
W25Q16_verilog_ise
- 一个基于w25q16的四通道flash读写操作控制器，spi传输。verilog语言编写，在ise的chipscop上验证可行，仅作学习参考-this is refrence about flash w25q16 controller ，writed by verilog
ECOP-13349069-03
- verilog语言实单周期cpu的设计，已经用ise测试、仿真通过。-verilog single cpu
Traffic-Controller
- 本代码为基于Spartan6的verilog交通控制灯代码，在ISE软件中仿真成功。-The code for the verilog code Spartan6 traffic control lights on in the ISE software emulation success.
Adder
- 本代码为用三种方法实现verilog加法器代码，在ISE中基于Spartan6仿真成功。-This code is used three methods to achieve adder verilog code, based on the success in the ISE Spartan6 simulation.
Booth4b
- booth 4 bits programmed by verilog and simulated using ISE software and no implemented
CPU(4)
- 基于ISE XILINX14.7开发的单周期CPU的基础指令实现代码 VERILOG-VERILOG implementation code base based on single-cycle instruction CPU ISE XILINX14.7 development of
counter2
- 附件包括两个内容1.采用Verilog编写的的十进制计数器的ISE工程2.代码文档一份。采用的软件平台是ISE13.3，硬件平台是Spartan-3E。-Appendix includes two contents of 1 written by Verilog decimal counter of the ISE project a 2 code document. The software platform is ISE13.3, the hardware platform is Spart
xvlijiance
- 附件包括四个内容1.采用Verilog编写的状态机实现序列检测的ISE工程2.代码文档一份3.原理说明4.使用说明。采用的软件平台是ISE13.3，硬件平台是Spartan-3E。-Accessories include four content of 1 by the state machine Verilog prepared realize sequence detection ISE works 2 code document a 3 principle that 4 instructi
car
- 基于Xilinx公司的ISE软件开发的智能循迹避障小车的源代码，用Verilog语言，传感器有红外传感器以及超声波传感器-Xilinx' s ISE-based software development intelligent car tracking avoidance source code, using Verilog language, the sensor has an infrared sensor and ultrasonic sensors
IIR
- 用Verilog实现一个IIR滤波器，并在ISE里面仿真。-Achieve an IIR filter with Verilog and simulation in ISE inside.
vga
- VGA控制器，Verilog描述，ISE工作环境-VGA controler
uart
- 利用xilinx 公司的ise软件基于verilog HDL实现UART控制程序-based on the xilinx ise and use verilog HDL language to achieve the purposes that control the uart.