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i2c_master_controller
- Verilig语言描述的I2C Mater控制器的IP核，已经过实践应用，适合于FPGA I2C接口设计应用。本IP核在Altera QII 15.1软件环境下综合，并且包含基于NiosII Gen2处理器的i2c软件驱动代码。-Verilig language I2C Mater described controller IP core, has been the practical application, suitable for FPGA I2C interface design app
modelsim-with-FPGA
- 使用modelsim对基于niosII处理器的FPGA开发系统进行软硬件联合仿真的方法。个人经验总结，在Altera QII 15.1环境下描述。希望能帮到正在做类似开发的工程师。-FPGA development system for use modelsim niosII processor-based hardware and software co-simulation approach. Personal Experience, at Altera QII 15.1 descr ipt
addafilter
- 基于NIOSii的数字滤波器，包括AD和DA的读取输出部分，包括C语言源码和verilog源工程-digital filter based on Nios2
fingerprint-identification
- 关于指纹识别的文章，基于niosii的FPGA平台，很不错-Fingerprint recognition on the article, very good
taxi
- 在NiosII上采用C语言实现编程，实现字符串显示滚动显示功能-On NiosII implemented using C language programming, string display scrolling display
kb
- 基于niosII系统的PS2键盘测试程序，测试PS2键盘与niosII内核的通信是否成功。该程序在Quartus自带的eclipes下编译运行。-Based nios II system PS2 keyboard test procedures, test PS2 keyboard and niosII kernel communication is successful. Compile and run under Quartus comes eclipes.
pinlvji-design-VHDL
- 使用Altera公司的EP2C35系列的FPGA芯片，利用SOPC-NIOSII-EP2C35开发板设计和仿真一个数字频率计，对1Hz~250KHz 的脉冲进行频率测量，采用等精度测量，即在所测量的整个频段内部，均可实现相同精度的测量，测量精度与频率无关，结果在数码管上显示-The use of Altera EP2C35 series FPGA chip using the SOPC-NIOSII-EP2C35 board design and simulation of a digital
SOPCIINIOSII-guiding-book
- SOPCIINIOSII实验指导书（第二版）和 实验操作手册，以ALTERA公司的NIOSII IP核为中心，详尽的说明NIOSII的SOPC设计，适用于SOPC-NIOSII EDA/SOPC实验开发平台的系列产品-SOPCIINIOSII experimental guide book (second edition) and the experimental operation manual to ALTERA company NIOSII IP core-centric, detaile
Niosii
- qsys的奇幻漂流系列，qsys学习资料-Qsys fantasy drifting series, qsys learning materials
niosii-triple-speed-ethernet-4sgx230-qsys-141
- 利用nios在altera的cyclone4sgx平台上实现一个三态以太网控制器(Implementation of a three state Ethernet controller using Nios)
music
- 实现了基于niosii的贪吃蛇音乐模块设计(music palyer function base on niosii)
can_loopback_test
- 实现了can控制器Verilog编程使用niosII 开发平台(Can controller Verilog programming, the use of niosII development platform)
SHA256_SYSTEM
- 利用硬件（可编程逻辑器件FPGA）实现密码算法SHA256，在FPGA中嵌入软核NIOSii，在NIOSii上进行软件编程。 硬件EDA工具为ALTERA的Quartus ii，软件IDE为eclipse（嵌在Quartua中）。(The hardware (programmable logic device FPGA) is used to implement the cryptographic algorithm SHA256, and the soft core NIOSii is em
SOPC开发快速入门教程中文版
- 本文为基于QuartusII和NiosII IDE的FPGA/SOPC开发资料，目的是为了尽快掌握FPGA/SOPC的开发流程，投入实践当中。(This paper develops data for FPGA/SOPC based on QuartusII and NiosII IDE. The purpose is to master the development process of FPGA/SOPC as soon as possible and put into practice.