搜索资源列表
setup_pll_design
- PLL design assitant, from M.H.Perrott, MIT
DE2_VGA3
- The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA is a clump formed by sticky particles adhering to an existing structure. In this design, we start with one pixel at the center of the screen and allow
Aidio
- 摘要：应用CXA1019S芯片完成接收机混频、中放、解调等的设计，并用芯片BU2614以PLL 频率合成的方法产生稳定的本振和控制输入调谐回路的谐振频率，从而实现电调谐。单片机采用 MCS-51系列对频率合成器BU2614进行控制，加上键盘、显示和存储器电路，可实现多种程控搜 索、电台存储等功能。-Abstract: The complete receiver chip CXA1019S mixer, amplifier, demodulator, such as design, a
smart
- 智能 全数字锁相环的设计 -smart all digital PLL design , very good
FrequencySynthesisbyPhaseLock
- 书籍频综和锁相环的Matlab源代码，对频综和锁相环的设计很有帮助；-Books PLL Frequency Synthesizer and the Matlab source code for PLL Frequency Synthesizer Design and helpful
matlab1
- 61549798pll_matlab[1]课程设计做的PLL,里面有关线性和非线性的都有,大家可以-61549798pll_matlab [1] course design done PLL, on the inside of both linear and nonlinear, we can
Springer.CMOS.PLL.Synthesizers.Analysis.and.Design
- Springer出版的非常好的CMOS PLL (锁相环设计)方面的资料.-Springer.CMOS.PLL.Synthesizers.Analysis.and.Design.Nov.2004.eBook-LinG
PhaseLockedLoop
- This tutorial starts with a simple conceptual model of an analog Phase-Locked Loop (PLL). Through elaboration it ends at a model of an all digital and fixed-point phase-locked loop. The final model can serve a starting point for code generation (both
PLL
- Practical Phase-Locked Loop Design.rar
adsx
- fpga的pll锁相设计，altera器件EP1s25的选用、设计-phase-locked pll of fpga design, altera devices EP1s25 selection, design
ad_pll
- fpga的pll锁相设计，altera器件EP1s25的选用、设计-phase-locked pll of fpga design, altera devices EP1s25 selection, design
simulink_communicationsystems
- 文件中包含有AM, DSB-SC, FM, PLL, Data Acquisition, Digital Data Transmission, PCM和Delta Modulation的simulink环境下的实现 -This project allows you to learn the communication systems in greater depth by giving you the reins to play with it ! It contains the simu
pll_manual
- 使用PLL design assistant程序进行PLL设计-PLL design using the PLL design assistant program
a
- PLL性能,仿真,设计handbook,总结了常用的PLL结构和性能,对设计PLL很有帮助-PLL performance,simulation,design handbook
dean_banerjee_pubns_-_pll_performance_simulation_
- PLL design and simulation
sanfenpin
- verilog 三分频 分频器是FPGA设计中使用频率非常高的基本设计之一，尽管在目前大部分设计中，广泛使用芯片厂家集成的锁相环资源，如altera 的PLL，Xilinx的DLL.来进行时钟的分频，倍频以及相移。-verilog-third of the frequency divider is a FPGA design, very high frequency of use, one of the basic design, although most of the designs in
StaticPLL
- 介绍FPGA中数字锁相环的设计方法和应用的文档-Introduction of Digital Phase-Locked Loop FPGA design methodology and application documents
AN177
- Digital PLL design, all technic how to develope eficiency digital locked loop. All descr iptions in English in details and examples
AN178
- Digital PLL design, all technic how to develope eficiency digital locked loop. All descr iptions in English in details and examples
an535
- Digital PLL design, all technic how to develope eficiency digital locked loop. All descr iptions in English in details and examples