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PLL_performance-_simulation_and_design
- PLL performance,simulation and design
NE564D
- 基于NE564D锁相环频率合成器的设计，毕业设计来的-Based NE564D PLL frequency synthesizer design, graduate design come
PLL_performance-_simulation_and_design
- PLL Algorithm, Perfomance and Design
program
- 锁相技术在测控、通信、数字信号处理等众多领域得到了广泛的应用。虚拟锁相环成为锁相环发展趋势之一，根据锁相环路的基本组成及原理，利用LabVIEW软件提供的强大的数值计算和信号分析等能力对锁相环进行设计。实验和仿真结果表明该软件锁相环具有较好的捕获和跟踪性能。利用软件实现的锁相环比硬件锁相环具有更好的灵活性和通用性，同时具有结构简单、参数设计灵活等优点。-Lock-in technique in many areas of monitoring and control, communication
VL7013-VLSI
- VL7013 VLSI FOR WIRELESS COMMUNICATION OBJECTIVES: • To study the design concepts of low noise amplifiers. • To study the various types of mixers designed for wireless communication. • To study and design PLL and VCO. •
E5_2_LoopDesign
- 基于matlab的关于通信系统中解调中载波锁相环的设计-On the design of the PLL demodulation in communication system of based on MATLAB
Phase-Locked-Loop
- PLL CODE IN VERILOG DESIGN
Example-s2-1
- 1.将随书所附光盘中的【Example-s2-1】目录拷贝到本地硬盘中 2.产生DQS模块 3.产生DQ模块 4.产生PLL模块 5.拷贝以上步骤生成的文件到子目录【Project】中 6.打开子目录【Project】中的DataPath.qpf工程，设计顶层模块 编译并查看编译结果-1. The accompanying CD-ROM with the book [Example-s2-1] catalog copy to your local hard drive
256-Shunt-Active-Power-Filter-under-unbalanced-ne
- This paper, focus on the study and design of a shunt active power (APF) filter for the compensation of harmonic currents and reactive power in polluted environment and under unbalanced network voltage. In APF design and control, p-q theory was often
mash11_only_canary
- mash2 for pll, fractional n frequency synthesizer of this code is very important, please download it and hope for help with your design.
Dean_PLL_sample_org
- Dean 的PLL Performance,Simulation and Design 这本书里实例matlab程序-Dean of the PLL Performance, Simulation and Design This book PLL filter matlab program to solve the
ADIsimPLL_V4_1_03_setup
- 最新的锁相环仿真工具，集成了ADI和HITTIC两大PLL厂家所有的器件库，可以为设计工程师提供大量仿真的参考。-The new design tools for PLL
5_Gray_Mean_Filter
- 均值滤波是典型的线性滤波算法，（Verilog HDL）设计所需的模块有： （1）带PLL的全局时钟管理模块 system_ctrl_pll.v （2）OV7725 COMS Sensor的初始化模块 i2c_timing_ctrl、I2C_OV7725_RGB565_Conofig （3）OV7725 COMS Sensor的视频信号采集模块COMS_Capture_RGB565 （4）SDRAM数据交互控制器Sdram_Control_2Port （5）VGA时序
pll_test
- PLL，即锁相环。是FPGA中的重要资源。由于一个复杂的FPGA系统往往需要多个不同频率，相位的时钟信号。所以，一个FPGA芯片中PLL的数量是衡量FPGA芯片能力的重要指标。FPGA的设计中，时钟系统的FPGA高速的设计极其重要，一个低抖动, 低延迟的系统时钟会增加FPGA设计的成功率。本例程调用Xilinx提供的PLL核来产生不同频率的时钟, 并把其中的一个时钟输出到FPGA外部IO上, 也就是开发板的SMA接口上。(PLL, pll. It's an important resource
kissContentmatrix
- charge pump for PLL at analog IC design div hr div B 文件列表 B ： div div()
dpll源程序
- 一种设计数字锁相环的思路，包含异或鉴相器、k模可逆计数器、脉冲加减计数器、N分频器等，实现相位的锁定。(A design of digital phase locked loop (PLL) consists of a phase discriminator, a K mode reversible counter, a pulse addition and subtraction counter, a N frequency divider and so on, to lock the pha
SSJRGAX
- charge pump for PLL at analog IC design div hr div B 文件列表 B ： div div()
sobel
- 由Verilog编写在FPGA实现sobel算法应用于图像边缘检测，工程文件可在quartus13.1以上版本打开；工程使用到ram、fifo、pll三种ip核，design文件夹下包含ram、fifo、vga控制以及串口收发和sobel算法模块，sim和doc文件夹下分别包含modelsim的仿真模块和仿真结果；测试时将200*200分辨率的图片用matlab文件夹下的matlab脚本压缩、二值化，再将生成文件中数据用串口发给FPGA，边缘检测结果会通过VGA输出。(Written by Ve