搜索资源列表
coder83
- 基于VHDL的8-3优先编码器模块，din0-din7八位二进制输入编码后输出三位编码结果。采用正逻辑设计，高电平有效。-8-3 priority encoder module, based on VHDL din0- din7 eight binary input encoded output three coding results. Adopt positive logic design, high level effectively.
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- 基础实验_04_优先编码器 ：8位输入3位输出高位优先-Experimental basis _04_ priority encoder: 8 input 3 output high priority
VHDL
- 3-8译码器 4-2优先编码器 4选1多路选择器-3-8 4-2 priority encoder decoder 4-to-1 multiplexer
VHDL-code
- 使用VHDL语言进行门电路，优先编码器，译码器，各进制计数器，数码管显示的编写，在QUARTUS ii上模拟可用-Gates using VHDL language, priority encoder, decoder, each binary counter, write digital display, analogue available on QUARTUS ii
Lab7_pencode83
- 8-3优先编码器的设计与实现.8-3优先编码器的真值表，本实验中用Verilog语句来描述.-Design and implementation of 8-3 priority encoder.8-3 priority encoder truth table, use the Verilog statement in this experiment to describe.
EDA
- 1.八进制计数器 2.八位右移寄存器 3.八位右移寄存器（并行输入串行输出） 4.半加 5.半加器 6.半减器 7.两数比较器 8.三数比较器 9.D触发器 10.T触发器 11.JK1触发器 12.JK触发器 13.三位全加器 14.SR触发器 15.T1触发器 16.三太门 17.有D触发器构成的6位2进制计数器 18.带同步置数的7进制减法计数器（6位右移寄存器） 19.二十四进制双向计数器 20.二选一 21
pri_encoder_using_if1
- priority encoder 16 to 4 using if with clk i`m add clk to another code-priority encoder 16 to 4 using if with clk i`m add clk to another code
8051
- 基于8051单片机的抢答器设计，有四种工作状态的切换，由两个开关控制，兼备记分牌的作用，硬件电路中有一个3线8线优先编码器，节省IO口-Responder 8051-based design, there are four working state switching, the role of the two switches control both the scoreboard, the hardware circuit has a 3-wire 8-wire priority encod
FPGA2
- 基于FPGA的8位输入，3位输出高位优先编码器-Based on the FPGA 8-bit input, three output high priority encoder
verilog-source-codes
- the attached programs are source codes of 4-bit ring counter, 16x1 mux, 8x3 priority encoder, 4x16 decoder, full subtractor using two half subtractors
VHDL
- 数字电路中常用的3线-8线译码器及8线-3线优先编码器的VHDL语言的功能描述-That is commonly used in digital circuit lines to 3-8 8 line to 3 line priority encoder decoder and the function of the VHDL language descr iption
coder_8_3
- 8 - 3 线 优 先 编 码 器 。高电平有效，高位到低位置位。高位优先级高于低位-8 3 line priority encoder. Active high, high to low bit. High priority than low
Router
- 5 Pin Router with Virtual Output Queues 32 bit arbiter optional encoder and decoder also included along with priority encoder-5 Pin Router with Virtual Output Queues 32 bit arbiter optional encoder and decoder also included along with priority encode
dual_priority_encoder2
- 这是一个组合电路，实现的是8位的优先编码器。-this is a combination circuit,Implement the eight priority encoder，
8bits
- 用Verilog语言模拟的8位优先编码器，可作为课堂作业实用，是完整工程代码-Using Verilog language simulation of the 8 priority encoder, can be used as a classroom operation, is a complete code
实验三（1）的指导书
- 8-3优先编码， 1、学会用Verilog语言的描述方式来设计电路； 2、熟悉8—3优先编码器，并用Verilog语言实现其功能； 3、掌握Cyclone系列FPGA的程序加载，熟练掌握将.sof文件加载到实验箱中，实现8—3优先编码器的效果。(8-3 priority coding, 1. Learn to design the circuit with Verilog descr iption; 2. Familiar with 8-3 priority encoder and i
05my_encode
- 器件EP4CE6F22C8N 4线-2线编码器 优先编码器(Device EP4CE6F22C8N lines to 4-2 encoder priority encoder)
kebenchengxu
- VHDL代码，一些课本的小程序。包含3线-8线译码器，4选1选择器，6层电梯，8线-3线编码器，8线-3线优先编码器，8选1，BCD-7段显示译码器真值表，半加器，摩尔状态机，数字频率计，数字时钟，同步计数器，序列检测器的设计，序列信号发生器，一般状态机等等。(The small program of some textbooks. Includes 3 -8 decoder, 4 1 selector, 6 elevator, line 8 Line 8 line -3 encoder, -3
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- VHDL代码，一些课本的小程序。包含3线-8线译码器，4选1选择器，6层电梯，8线-3线编码器，8线-3线优先编码器，8选1，BCD-7段显示译码器真值表，半加器，摩尔状态机，数字频率计，数字时钟，序列检测器的设计，一般状态机等等。(VHDL code, some textbooks for small programs. Includes 3 -8 decoder, 4 1 selector, 6 elevator, line 8 Line 8 line -3 encoder, -3 prio
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- VHDL代码，一些课本的小程序。包含3线-8线译码器，4选1选择器，6层电梯，8线-3线编码器，8线-3线优先编码器，8选1，BCD-7段显示译码器真值表，半加器，摩尔状态机，数字时钟，序列检测器的设计，一般状态机等等。(VHDL code, some textbooks for small programs. It includes 3 line -8 line decoder, 4 selector 1 selector, 6 elevator, 8 line -3 encoder, 8 l