搜索资源列表
sdram_mdl
- verilog编写的对SDRAM的控制的源代码，开发FPGA/CPLD-verilog SDRAM write control of the source code, development FPGA/CPLD
source
- SDRAM 控制, 用於SDRAM上 的代碼-SDRAM Control
UART_DMA
- 实用串口与SDRAM控制接口VHDL语言程序代码-Utility serial port and SDRAM control interface VHDL language code
DDR-SDRAM
- 本应用指南描述了在 Virtex™ -4 XC4VLX25 FF668 -10C 器件中实现的 DDR SDRAM 控制器。该实现运用了直接时钟控制技术来实现数据采集，并采用自动校准电路来调整数据线上的延迟。-This application note describes a Virtex ™ -4 XC4VLX25 FF668-10C to implement the DDR SDRAM device controller. The clock control to ach
ddr_sdr
- DDR SDRAM 控制器 包含测试向量和仿真模型-DDR SDRAM control
project1_supplemental1
- these are projects based on verilog like memory control, sdram control etc-these are projects based on verilog like memory control, sdram control etc..
SDRAM-Modelsim
- SDRAM读写控制的实现与Modelsim仿真-SDRAM read and write control to achieve with Modelsim Simulation
sdram
- SDRAM 的读写，在仿真版上测试过的 可以用，源码+控制逻辑-SDRAM read and write, tested in the simulation version Can use the source code+ control logic
SDRAM
- 在ISE环境下对SDRAM(异步动态存储器)的控制模块设计。-In the ISE environment of SDRAM ( asynchronous DRAM ) control module design.
vhdl_sdram
- Altera Sdram vhdl 控制代码-Altera Sdram vhdl control code
sdr_sdram
- 用FPGA实现SDRAM的控制，主要是将SDRAM的时序搞懂，这个很好做出来了。-Using FPGA realize SDRAM control, mainly the SDRAM timing out, this is very good do.
sdram
- SDram的读写控制。站长我是一名初学者，而且对其很感兴趣，但作为一个初学者起始是万般艰难的，我就只有这一源代码，奉上。望转正！万分谢谢。-The control SDram, reading and writing
Sdram_Control_4Port
- Sdram Control 4Port Sdram Control 4Port
sdram-ctrl
- FPGA sdram 全页模式控制，用verilog语言写的，非常的精简，控制方便-FPGA sdram full-page mode control, written in verilog language is compact, easy to control
sdram_control
- sdram控制,完整的sdram读写控制代码，操作简明易懂。带模拟输入，可- sdram control.write and read
1_sdram_controller
- 这是altera公司的sdram IP core的用户使用指南，可以参考这个自己开发-sdram control ip core
sdram_mdl
- 用Verilog HDL编写的SDRAM控制程序，在DE2-70上测试通过，有很大的参考价值。-SDRAM control program written using Verilog HDL DE2-70 test passes, great reference value.
Altera-SDRAM_controller-IP-CORE
- ALTRA官方提供的SDRAM的控制内核，VHDL和VERILOG版本都有，希望对大家有用-The ALTRA official SDRAM control kernel, VHDL and VERILOG version have the hope that useful
SDRAM_FPGA
- 这个是SDRAM的控制程序，包括包括UART和FIFO模块，适合FPGA开发人员看，也适合初学者学习。-This is the SDRAM control procedures, including including UART and FIFO module, suitable for FPGA developers look, but also suitable for beginners to learn.
SDRAM-dataset
- SDRAM详细资料集，还有FPGA控制SDRAM的读写实例，对于想要深入研究FPGA的朋友非常有帮助-SDRAM detailed data sets, as well as examples of FPGA control SDRAM read and write, who want in-depth study on FPGA friends very helpful! !