搜索资源列表
06168353
- The Fast Fourier Transform (FFT) is one of the rudimentary operations in field of digital signal and image processing. Some of the very vital applications of the fast fourier transform include Signal analysis, Sound filtering, Data compressio
half_adder
- 半加器的VHDL实现，包括Testbench的编写，可供新手参考-Half Adder VHDL Testbench
ic74f539
- ic74f539芯片的VHDL实现，包含Testbench编写，可供新手参考。-ic74f539 VHDL Testbench
ic74hc574
- ic74hc574芯片VHDL功能实现，包括Testbench编写，可供新手参考。-ic74hc574 VHDL Testbench
Multiplier
- 我是2014级复旦的研究生。这是用VHDL语言设计的任意的M乘以N位的乘法器。设计中，被除数和乘数的位数是通过参数来设置的，可由你来修改。我已写好了testbench。可放心使用。-I am a 2014 graduate of Fudan University. This is an arbitrary M VHDL language designed by N-bit multiplier. Design, the dividend and the median multiplier is
TEXIO
- TEXIO study testbench passed VHDL FPGA CPLD simulation Altera quartus
testbench_top_level.vhd
- testbench for top level, vhdl, audio synthesizer, top level
CAVLE-h264
- 本压缩文件包含了h.264压缩算法中的CAVLE的编解码模块（Verilog和VHDL两个版本），包含有仿真的testbench测试文件，综合后可以直接使用-The compressed file contains the h.264 compression algorithm CAVLE codec module (Verilog and VHDL both versions), including a simulation testbench test file, can be used d
DIVIDER
- 大家好，我是复旦大学的研究生。本资源是一个基于VHDL语言的M位除以N位的除法器。其中M/N ，商M位，余数是N位的。以Moim设计验证和验证。压缩包里有除法器的源文件和testbench。可加入工程，直接测试。鄙人测试都是无错误的。愿尊驾下载后，积极评价，以便于相互交流，学习。O(∩_∩)O谢谢.2015年5月7日于芬兰，图尔库。-Hello everyone, I am a graduate student at Fudan University. This resource is base
VHDL_Multiplier
- 三种 VHDL 实现乘法器的方法，可以用于学习FPGA的时序、组合电路，同时附带了 TestBench 程序-Three kinds of methods to achieve multiplier in VHDL, with TestBench
串并转换
- vhdl实现串并转换，其中附有源程序和testbench程序，可以用modelsim仿真
ddr2_controller
- A controller for DDR2 on FPGA with vhdl, content testbench, model and textfile-generation/data-detection using python.
debouncer_vhdl
- RTL and testbench implementations for a switch debouncer with support for multiple switches, written in VHDL.
fft_small_tb
- vhdl testbench for 8pt fft
SPI-master-P-tb
- SPI master VHDL realisation Also contains TestBench
uartlvds
- UART VHDL sources with FIFO-UART VHDL sources with FIFO,baudrate,receiver,transmitter,register,testbench
fpu_double
- The Verilog version of the code is in folder “fpu_double”, and the VHDL version is in folder “double_fpu”. There is a readme file in each folder, and a testbench file to simulate each core. These cores are designed to meet the IEEE 754 standard f
OpenMIPS_VHDL_study_v1.0
- 10天实现OPENMIPS处理器-VHDL版[内有详细代码，testbench和设计文档，十天教你学会MIPS架构CPU设计]-10 days to achieve the OPENMIPS processor-VHDL version [within a detailed code, testbench and design documents, ten days to teach you to learn MIPS architecture CPU design]
convolution
- 卷积 严格遵守时序的一维卷积运算，用testbench测试了-convolution write a VHDL file to compute one-dimensional convolution latency 14
VHDL-Code-and-TestBench-Code
- 实现了三个功能电路的程序：时钟分频电路；移位寄存器；序列检测器。-Including three parts:frequency divider shifting register sequential detector