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71477212NiosII_uart
- 串口sopc uart实现串口功能，包含帧的开始字节，命令字节-Serial sopc uart serial implementation features, including frame start byte, command byte
UART_DESIGN
- The use of hardware descr iption languages (HDLs) is becoming increasingly common for designing and verifying FPGA designs. Behavior level descr iption not only increases design productivity, but also provides unique advantages for design verif
UART
- UART通信协议的硬件描述语言代码，用与FPGA的总线接口开发-UART communication protocol of the hardware descr iption language code, using the bus interface with the FPGA development
uart_ise_vhdl
- fpga里实现 uart 经典 vhdl语言写的 ise工程文件-fpga implementation in vhdl language classic uart of ise project file
first_cpu
- nios ii cpu核，包含通用IO口、sdram、flash、uart-nios ii cpu、genernal io port、sdram、falsh、uart
UART
- UART是一种广泛应用于短距离、低速、低成本通信的串行传输接口.由于常用UART芯片比较复杂且移植性差,提出一种采用可编程器件FPGA实现UART的方法, 实现了对UART的模块化设计.首先简要介绍UART的基本特点,然后依据其系统组成设计顶层模块,再采用有限状态机设计接收器模块和发送器模块,所有功能的实现全部采用VHDL进行描述,并用Modelsim软件对所有模块仿真实现.最后将UART的核心功能集成到FPGA上,使整体设计紧凑,小巧,实现的UART功能稳定、可靠. -UART is a wi
uart
- 基于FPGA的uart源代码，异步串行通信，vhdl书写的。-uart codes。write with vhdl.
uart_receiver
- This UART Receiver interface C code Tested on Sparton 3 xilinx FPGA.-This is UART Receiver interface C code Tested on Sparton 3 xilinx FPGA.
UART
- Hardware Design with VHDL Design Example: UART
uart
- uart send resive module
UART
- A badic controller for the UART. It incorporates a -- transmit and receive FIFO (from Max+Plus II s MegaWizard -- plug-in manager). Note that no checking is done to see -- whether the FIFOs are overflowing or not. This strictly -- handles the
CameraDriver
- This module use OV7620 digital camera on the 24-bit RBG (8:8:8) data and display that in RS232 uart interface
uart_module
- 实现精简的uart串口,格式起始位+8bit数据位+可配置的奇偶校验位+停止位-implement a smart UART interface
miniuart.tar
- 用VHDL描述的简单UART接口，能正确实现简单的功能-VHDL descr iption with a simple UART interface
uart
- fpga内嵌入双向串行通讯口 传输波特率可变 可通过查询方式确定发送接收状态 内置256字节发送接收缓冲区 -serial communication
UARTcode
- 串口UART通用异步接收/发送器的VHDL 源代码-Serial UART code
uart16450
- uart 16450合集,xilin altera lattice-collection of uart controller 16450
cp_uart_6
- 用CPLD驱动UART转USB芯片CP2102的verilog代码，与PC通信 包括CP2102的配置 驱动等-Using CPLD to drive the USB-UART CP2102 interface. verilog code, then communicate with PC, including the configuration and drivers, etc.
s7enable_send0x55_UART_9600
- 最简单的UART发送程序，vhdl编写，系统时钟40M，波特率9600，外Load有效（一个高脉冲）即向PC发送一个字节0X-UART to send the simplest procedures, vhdl prepared, the system clock 40M, baud rate 9600, outside the Load effective (a high-pulse) to the PC sends a byte 0X55
Uart
- Uart总线，VHDL语言，硬件描述语言源码-Uart bus, VHDL language, VHDL source code