搜索资源列表
HCIUART
- 蓝牙HCI—UART与并口的FPGA控制接口设计-Bluetooth HCI-UART and parallel port control interface of the FPGA design
UART
- URAT 部分VHDL源码 大家多多支持 哈哈 -VHDL source URAT part of U.S. support of Haha
vhdl
- 经过验证的UART硬件描述语言（VHDL）代码，非常实用。-Verified UART hardware descr iption language (VHDL) code, very useful.
btm_communication
- 自己项目中用到的verilog UART程序。-Their own projects verilog UART procedure used.
uart
- 通用穿行通信控制器，可以直接使用，在quartsII下开发-GM through communications controller, can be directly used in developing quartsII
uart_regs
- UART串行通讯FPGA实现，新手上道请多多指教-FPGA realization of UART serial communication, and newcomers on the Road, please advice
uart
- 串口通讯rs232,时钟频率为40Mhz,波特率为19200,没有奇偶校验,在xilinx XC3S200A板子上验证过.-Serial communication rs232, clock frequency of 40Mhz, the baud rate to 19200, no parity, in the board on xilinx XC3S200A verified.
uart
- 用vhdl实现的串口通信程序,可以综合并下载到FPGA运行.-Achieved using VHDL serial communication procedures, can be synthesized and downloaded to the FPGA to run.
x1Altera_uart_VHDL
- 经典UART程序，通用异步收发器设计的vhdl语言,帮助大家学习UART知识-UART classical procedures, UART VHDL design language, to help everyone study UART knowledge
x3uart
- 学习UART知识，经典UART程序，通用异步收发器设计的vhdl语言-UART study of knowledge, classical UART procedures, UART VHDL design language
test_uart
- uart VHDL code : include tx,rx,parity bit control
rxd
- VHDL语言写的UART通信接收端程序，适用于RS232协议-VHDL language the receiving end of the UART communication procedures, applicable to RS232 protocol
uartfifo
- FPGA串口代码实现，带串口模块控制程序-Realization of UART in FPGA, with UART module control codes.
uart_zhiwen
- RS232的UART编程，包括波特率发生器模块，串口接受模块，串口发送模块-RS232 programming the UART, including the baud rate generator module, serial module to receive, send serial module
uart16750_latest.tar
- Implements a 16550/16750 UART core
kp_uart
- This UART and LCD interface C code Tested on Sparton 3 xilinx FPGA.-This is UART and LCD interface C code Tested on Sparton 3 xilinx FPGA.
UARTtransmitter
- UART Transmitter. VHDL code and its testbench.
EP1C3_12_7_SPCTR
- 基于FPGA的信号采集及频谱分析，用VHDL编写，压缩包里是Quartus下的工程。AD采样用状态机实现，并存入LPM_RAM。设计了一个UART模块（也是状态机实现的），可将数据发到ＰＣ机上。-FPGA-based signal acquisition and spectral analysis, prepared with VHDL, Quartus compression bag is the next project. AD sampling state machine used to
traffic_light
- 交通灯控制系统，包括UART模块的设计和实现-Traffic light control system, including the UART module design and implementation of
03.EDK8.2
- 使用xilinx virtex4芯片，设计环境为EDK，其中包含uart,片外sram操作，flash操作，DDR SDRAM操作，MAC自发自收，audio，video等试验-Xilinx virtex4 use chip design environment for the EDK, which contains the uart, chip sram operation, flash operation, DDR SDRAM operation, MAC spontaneous self-