搜索资源列表
dds_vhdl
- 该源码为VHDL语言编写DDS生产正弦波信号源码-The DDS source for the VHDL language production of sine wave signal source
VHDLseven-segmentdecoder
- VHDL在液晶显示上的七段译码器源码,应用于FPGA,ASIC等硬件设计-VHDL in the seven-segment liquid crystal display on the decoder source code, used in FPGA, ASIC and other hardware design
counter_four
- 模拟了半加器和全加器的vhdl语言源码。-model half add and full add mechine vhdl code
alu_all
- VHDL设计的流水CPU,开发环境是quartusII,代码经过验证，完全是自主开发的源码-A CPU designed by VHDL with PIPE
vhdl_programming_classical_source
- vhdl程序设计经典源码vhdl programming classical source-vhdl programming classic source vhdl programming classical source
verilog
- 里面包含了大量VHDL的源码程序，赶快下载来分析分析吧 希望对大家有用哈-Which contains a large number of VHDL source program to analyze the analysis quickly download it hope to be useful Kazakhstan...
CDPlayersources
- 全套日本CD Player的FPGA设计制作源码，用VHDL编写，具有很好的参考价值。-Japanese CD Player complete set of FPGA design source code, written using VHDL with a good reference value.
8.6DAC0832
- FPGA中用VHDL编写的DA8032的接口电路及程序源码-DA8032 prepared using VHDL FPGA interface circuit and program source code
8.7TLC7524
- FPGA中使用VHDL语言编写的TLC7524的接口电路及程序源码-FPGA using VHDL language of the TLC7524 the interface circuit and program source code
SPI_verilog_vhdl
- spi接口的VHDL和Verilog-HDL源码-VHDL and Verilog-HDL code for spi
VHD_Veri_spi
- 一个强大的符合SPI规范的VHDL/Verilog源码文件，传输模式和时钟相位均可以指定，采用同步时钟设计，可以工作在很高的频率下。支持主机及从机模式，强烈推荐使用！-A strong line with SPI standard VHDL/Verilog source files, transfer mode, and clock phase are to specify, using synchronous clock design can work in very high frequen
SPI
- SPI总线通信模块，经测试验证通过的源码-SPI vhdl source code
freqtest_dec
- 用VHDL设计了一个频率计，给出了各模块的详细源码，并给出了注解，对初学者及课程设计有帮助。-VHD designed with a frequency counter, gives the details of each module source code, and gives notes on programs designed for beginners and helpful.
RS232_ysd
- 串口接口控制器参考设计VHDL代码,方便开发FPGA人员进行串口的开发，是一个不错的源码解压安装后可在quartus里例化使用-Serial interface controller reference design VHDL code, facilitate the development of FPGA serial port staff development, is a good source decompression after installation in case of use
VGA_ysd
- vga接口控制器参考设计VHDL代码,方便开发FPGA人员进行vga的开发，是一个不错的源码解压安装后可在quartus里例化使用-vga interface controller reference design for VHDL code, and facilitate the development of FPGA vga staff development, is a good source installed after decompression in the case of usi
jiaotongled
- 该源码用vhdl语言制作了一个简单的交通灯，方便大家学习-The source vhdl language produced by a simple traffic light, facilitate learning ~ ~
alu
- 加法器源码 CPU设计专用 VHDL实现-Source adder VHDL CPU designed to achieve specific
cpudesignandreport
- 简单CPU VHDL实现 包含全部源码和报告-Simple CPU VHDL implementation and report that contains all the source code
eluosifangkuai
- 俄罗斯方块vhdl实现源码 硬件altera的FPGA 键盘 16*16点阵 数码管-Tetris source vhdl implementation
8052-vga
- 用VHDL语言设计的，可以用显示器显示汉字或者字符的源码程序-Designed with the VHDL language can be used to display Chinese characters or character of the source program! ! !