搜索资源列表
V_ADC_SPCTR_ANALZ
- 这是用VHDL写的高速AD采样分析设计的源码-It is written in high-speed AD VHDL design source sampling and analysis
music1
- VHDL 多功能数字钟源码音乐模块2，自扒简谱-Multi-function digital clock source VHDL music module 2, since the expense of musical notation
controlvhdl
- 一个四位微程序控制器的指令译码器源码，运用VHDL语言实现。-A four micro-program controller instruction decoder source code, the use of VHDL language.
HDB3
- 基于FPGA的HDB3编码 利用VHDL实现的源码-The HDB3 code based on FPGA implementation using VHDL source code
rom
- 该源码是基于查找表的VHDL代码实现DDS-The source code is based on the VHDL code look-up table DDS
uart_vhdl_verilog
- 串口FPGA的实现源码，VHDL和Verlog两种语言源代码。-UART FPGA implementation source code, VHDL and Verlog two languages source code .
dds_xu
- 直接数字频率合成器的VHDL完全源码，经测试可以正常使用，仿真正常-Direct Digital Frequency Synthesizer
CoreSPI_21_eval
- SPI IP核源码，包括Verilog和VHDL两种语言源码-SPI IP core source code, including the two languages Verilog and VHDL source code
CLOCK
- VHDL的电子闹钟源码。适合初学者，因为我也是初学者。囧-VHDL source code of electronic alarm clock. For beginners, because I am also beginner.囧
VGA_Core
- 基于FPGA的VGA显示系统的开发设计，一段VHDL写的很好的VGA驱动源码。-FPGA-based VGA display system design, a VHDL VGA driver to write a good source.
scpu
- 一些零散而简单的CPU功能部件，一部分源码是放在TXT文件中，只要改成VHDL格式就可以使用。-Some scattered and simple CPU features, part of the source is placed in TXT file into VHDL format as long as you can use.
crc
- 基于VHDL的CRC编码器的CRC的生成模块源码。-The CRC based on VHDL CRC encoder source code generation module.
crc
- 基于VHDL的CRC编码器的检错模块的源码-The VHDL-based CRC error detection encoder module source
Traffic_Light
- 用VHDL实现交通灯设计里面有工程和源码-Design with VHDL implementation of traffic lights there are projects and source code
FPGAVHDLeclock
- 数字钟设计报告 包括源码 仿真 设计原理等 vhdl编写 -vhdl fpga eclock
VHDLshixianCPU2
- vhdl实现cpu用verilog写的8位CPU源码，通过汇编语言可以实现加减乘左移右移等运算。并通过ASC流程可以模拟出其内部电路结构。代码，截图，readme在文件夹中-With 8-bit CPU to write verilog source code, assembly language can be achieved through the addition, subtraction and other operations right left. ASC process throu
shuzipinluji
- 基于fpga的数字频率计的vhdl设计源码-Fpga-based digital frequency meter vhdl design source
vhdl_0007
- 国家晶片系统设计中心的VHDL设计资料，包括VHDL语法，同步约束，频率设计，系统模拟和源码实验等高难技术的讲解-National Chip Implementation Center of the VHDL design, including VHDL syntax, synchronization constraints, frequency design, system simulation and difficult to source high technology to explai
anna-y0802
- 压缩文件内含有VHDL和VERILOG编写的SDRM控制源码，已通过编译，均可直接使用。-Zip file contains VHDL and VERILOG source code written in SDRM control, has passed the compilation, can be used directly.
vhdlClock
- VHDL编写的电子时钟程序，经仿真正确，包含源码-Electronic clock program written in VHDL, the simulation is correct, including source code