搜索资源列表
FPGA-FIR
- FIR滤波器，算法，采用VHDL编程语言，算法比较简单，希望对大家有所帮助。-FIR filter algorithm, using VHDL programming language, the algorithm is simple, we want to help.
my_kmp_matching
- KMP算法的Verilog HDL实现，模式串从模块的外部输入，计算next函数，然后进行KMP匹配。有仿真。环境为Quartus II 8.0 Web Edition。-Verilog HDL implementation KMP algorithm, pattern string from the module' s external input, calculate next function, then KMP matching. A simulation. Environment
PID
- 流量控制 正文 PID算法的自动控制 fpga-Flow control body of the PID algorithm for the automatic control
FPGA-PID-
- FPGA闭环控制电路积分分离式PID算法子程序 算法函数 中断函数-Integral closed loop control circuit FPGA PID algorithm separate interrupt function subroutine algorithm function
mid-filter
- mid-filter 中值滤波算法的原理及核心代码 word版-mid-filter median filter and the core principles of the code word version
AES
- 详细描述了AES加密算法的过程及S盒变换，用VHDL语言描述，通俗易懂-AES encryption algorithm is described in detail the process and transform S box, with the VHDL language to describe, easy to understand
vhdl
- 使用vhdl并行算法实现洗衣机水位，指示灯的控制调节-Vhdl parallel algorithm using washing machine water level control adjustment indicator
NCO
- 关于FPGA设计实现NCO，包括查找表法和CORDIC算法的改进-FPGA design and implementation on the NCO, including the look-up table method and the CORDIC Algorithm
ANNs
- 人工神经网络（ArtificialNeuralNetworks，简写为ANNs）也简称为神经网络（NNs）或称作连接模型（ConnectionistModel），它是一种模范动物神经网络行为特征，进行分布式并行信息处理的算法数学模型。这种网络依靠系统的复杂程度，通过调整内部大量节点之间相互连接的关系，从而达到处理信息的目的。 -Artificial neural network (ArtificialNeuralNetworks, abbreviated as ANNs) also refe
matlab-gmsk
- 基于matlab和vhdl的通信原理gmsk调制算法，主要包括GMSK相位路径的计算,GMSK眼图的仿真以验证相位计算的正确性,正余弦表的量化及bin文件的生成,以及用VHDL硬件语言所描述的基于EPM7128的地址逻辑.-Matlab and vhdl based on the principle gmsk Modulation of communication, including GMSK phase path calculation, GMSK eye diagrams of the s
Description-of-DES-with-VHDL
- 用VHDL描述DES算法 用硬件的方式DES加解密 体现了硬件编程人一般思想-DES algorithm using VHDL descr iption of the way with hardware DES encryption and decryption hardware programming reflects the general thinking of people
SG_FPGA
- 2006年电子设计竞赛二等奖，多功能函数、信号发生器核心器件FPGA内部的原理图，主要模块用VHDL代码描述，包括PLL、相位累加器、波形算法和正弦波查找表，可实现0.005Hz~20MHz的多波形信号产生，频率步进值0.005，输出接100MSPS速率的DAC--AD9762-Electronic Design Competition 2006, second prize, multi-function signal generator within the core of the devic
BT656_RGB
- BT656转RGB的算法实现代码，使用VORILOG语言编写-BT656-->RGB, verilog
matlab-genetic-algorithm
- matlab用法 主要用于线性规划，非线性规划，解决优化问题，作出最合理的决策等遗传算法程序-matlab usage is mainly used for linear programming, nonlinear programming to solve optimization problems, make the most rational decision-making, genetic algorithm
Digital-Signal-Processing-with-FPGA
- FPGA结合DSP设计，如FIR、IIR滤波器，CORDIC算法,多重采样率信号处理，FFT,有对应的VHDL/Verilog 代码code-FPGA Combines with DSP, FIR 、IIR Digital Filters,CORDIC,FFT,Adaptive Filters，VHDL/Verilog code
dct
- 基于FPGA的图像压缩算法程序，自己写的，可以参考一下-FPGA-based image compression algorithm, write your own, you can refer to
VHDL-test-code-divider
- VHDL实验代码：除法器，是一个基于VHDL语言开发的小程序，是关于除法的算法，比较实用-VHDL test code: divider, is a VHDL-based language developed by a small program, on the division algorithm, more practical
VHDL
- 基于VHDL的数字倍频器设计，这里只提供个算法，希望对你的编程有所启发。-Vhdl based on the number of times the frequency of the design,Here only to provide an algorithm, hope for your programming has been inspired.
CRC-Parallel-Computation
- 用软件实现CRC校验码计算很难满足高速数据通信的要求， 基于硬件的实现方法中， 有串行经典算法LFSR,电路以及由软件算法推导出来的其它各种并行计算方法。以经典的LFSR,电路为基础， 研究了按字节并行计算CRC校验码的原理.-Implemented in software CRC checksum calculation is difficult to meet the requirements of high-speed data communications, hardware-based
Cordic_VHDL
- Cordic算法的VHDL实现, 初学者可以体验下算法硬件编程-Cordic algorithm of VHDL, beginners can experience the next hardware programming algorithm