搜索资源列表
cic_bf
- vhdl编写的梳妆滤波器和蝶形运算的算法。蝶形计算通过调用fpga内部的乘法器实现。-dressing prepared vhdl butterfly filters and computing algorithms. Butterfly calculation by calling the multiplier to achieve within the fpga.
fft
- 关于vhdl-FPGA实现fft算法的模块-MATLAB VHDL ADN EDA
VHDL_butterfly
- vhdl编写的蝶形算法程序,供大家参考~~~可用于fft的实现-vhdl butterfly algorithm written procedures for your reference ~ ~ ~ can be used for the realization of fft
lunwen
- 潘明海 刘英哲 于维双 (论文) 中文摘要: 本文讨论了一种可在FPGA上实现的FFT结构。该结构采用基于流水线结构和快速并行乘法器的蝶形处理器。乘法器采用改进的Booth算法,简化了部分积符号扩展,使用Wallace树结构和4-2压缩器对部分积归约。以8点复点FFT为实例设计相应的控制电路。使用VHDL语言完成设计,并综合到FPGA中。从综合的结果看该结构可在XC4025E-2上以52MHz的时钟高速运行。在此基础上易于扩展为大点数FFT运算结构。 -Pan Mingha
hamingFPGA
- 本文介绍了汉明编码与译码通过FPGA器件来实现,介绍了使用VHDL语言编程的基本算法!-This article describes the Hamming encoding and decoding through the FPGA device to implement, introduced the use of VHDL programming language is the basic algorithm!
use_3_shoft
- SHA-1的verilog程序,经过优化的了,希望可以对大家有帮助-SHA-1 of the verilog program, optimized, and hope that we can help you
h_adder
- 一种半加器的算法,是基于VHDL软件仿真。请大家下载参考!-A full-adder algorithm is based on the VHDL software emulation. Please download the reference!
interface
- 采用Cyclone EP1C3,VHDL程序算法实现了信号波形的实时采样并回放,同时能测量时域信号的频率,通过与MCU的8位并行接口,进行相互通信。-Using Cyclone EP1C3, VHDL program algorithm of the signal waveform of real-time sampling and playback at the same time capable of measuring the frequency of the signal in time
VHDLmath
- 这是一篇关于VHDL各种算术算法的文章,希望对各位有帮助 -This is a variety of mathematical algorithms on the VHDL articles, want to be helpful
VHDLkejian
- EDA技术从某种意义上说:学习一种通过软件的方法来高效地完成硬件设计的计算机技术__------VHDL文字说明的系统的功能——系统逻辑描述(算法)——图、VHDL语言(用一套计算机能处理的语言来描述设计结果和设计要求)。 -EDA technology from a sense: to learn a software approach to efficiently complete the hardware design of computer technology __------ V
sha_algo
- SHA core cryptographic core
DesignofFloatingPointCalculatorBasedonFPGA
- 给出系统的整体框架设计和各模块的实现,包括芯片的选择、各模块之间的时序以及控制、每个运算模块详细的工作原理和算法设计流程;通过VHDL语言编程来实现浮点数的加减、乘除和开方等基本运算功能;在Xilinx ISE环境下,对系统的主要模块进行开发设计及功能仿真,验证 了基于FPGA的浮点运算。 -The overall framework of system design and realization of each module which contain selection of ch
myspu
- vhdl编写的cpu程序,直接用状态机编写的,没有微指令过程,基本算法都包含,新手学习用-vhdl cpu written procedures for the preparation of a state machine directly, without microcode process, the basic algorithms are included, beginners learn to use
booth
- 布斯公式求补码乘法的算法,用VHDL语言编写-booth algrithm, work out the 2 s complement mulitplier using VHDL
DES
- VHDL语言编写的DES算法,可以参考一下。 -VHDL language of the DES algorithm for reference.
MIPS_CPU
- MIPS结构的CPU,采用VHDL编码,附带验证程序,能够跑题hash算法,流水灯,求π程序-MIPS structure of the CPU, using VHDL coding, with the verification process, to get off track and hash algorithms, water lights, find π procedures
p8fft
- 8点位数可变FFT算法的VHDL语言 已通过quartusii编译仿真-8-digit variable FFT algorithm VHDL, simulation has been compiled by quartusii
Df3
- fpgafft 用 实现dsp 的fft算法 其中有几个文档文件和用vhdl写的1024点 代码-fpgafft dsp with the fft algorithm to achieve a number of documents including documents and written with a vhdl code for 1024 points
qj
- 全加器。使用Vhdl语言实现数字电路全加器功能,算法比较简单,供初学者参考。-Full adder. Digital circuits using Vhdl language full adder function, the algorithm is relatively simple for advanced users.