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UART_final
- 利用vhdl硬件描述语言，模拟异步通用串行接口UART的通信方式，已在fpga上实际测试，通信性能不错，有一定的参考学习价值！-Using vhdl hardware descr iption language, simulated UART asynchronous serial interface common means of communication, the actual test in fpga, communication performance is good, there i
handset
- 利用硬件描述语言vhdl模拟实现与9针ps2手柄的串行通信，完成手柄输入信号的采集。-Vhdl simulation using hardware descr iption language to achieve ps2 with 9-pin serial communication handle, the handle to complete the input signal acquisition.
chuankou
- 实现FPGA与电脑串口通信，开发语言为VHDL-Serial communication with the computer of FPGA, VHDL language development
Asyn_commu_cont-
- VHDL编写的异步通信控制器源码，实现数据的异步收发。-Asynchronous communication controller coded with VHDL.
shunmaguanxianshidianlu
- 用VHDL语言编写一个八位数码管显示电路，每个数码管的八个段分别连在一起，八个数码管分别由八个选通信号选择。被选通的数码管显示数据，其余关闭-With the VHDL language to write a eight digital tube display circuit, each digital tube eight segments are connected together, the eight digital tube are respectively composed of
PRBS
- 代码是伪随机数生成和检测的模块，用于通信行业的FPGA编程。包括VHDL和Verilog两种语言的版本。用于做接口测试。-This module generates or check a PRBS pattern.
serial
- 用VHDL实现串口与电脑通信，已调试过，没错误-it can be used to commuciate serial with computer
frequency-meter-of-same-precision
- 本系统采用了以Altera芯片EPF10K10LC84-4和单片机仿真器伟福H51/S POD-H8X5X 为核心，同时辅有8位七段数码管和7219数码管驱动芯片。设计使用max+plus2，keil3和伟福开发环境，其中FPGA计数功能，FPGA与单片机的接口通信，单片机计算数据并驱动显示模块等功能。 系统实现了4hz~12Mhz频率的测量，并利用科学计数法显示。测量相对误差在0.005 以内，每个频段均显示6位有效数字。 本系统的特点在于高精度，显示界面科学友好。硬件部分VHD
Verilog
- 无线通信FPGA设计的VHDL编程，里面的内容很详细-wire communication VHDL program
spi_master
- 用VHDL编写的一个SPI主机程序，SPI模块采用最常用的模式0方式（即CPOL=0,CPHA=0）通信。文件内含测试文档，已在Modelsim6.5上测试通过，可在FPGA上直接调用。-A SPI Master code edited by VHDL language,the SPI modul use 0 MODE(i.e CPOL=0,CPHA=0)to communicate with the SPI Slave.and there is a testbench in the file
hdlc
- 这是VHDL语言编写的实现 HDLC通信协议的源代码-This is the HDLC communications protocol source code written in VHDL language
RS232-bus-protocol
- 有fpga VHDL原程序 锁脚文件 及下载文件 ，及uart通信协议-Fpga the VHDL program locks the foot of the original files and download files, and uart communication protocol
ASK
- 利用VHDL搭建通信系统（2进制调幅键控） 你可以熟悉学习通信系统-this is the code that is used for comunication about ASK
baud
- UART 异步通信串口协议的VHDL实现包括3个基本模块：时钟分频、接收模块和发送模块-UART asynchronous serial interface protocol VHDL consists of three basic modules: clock divider, the receiver module and transmit module
Rwummayiie
- 研究了传统误码仪的工作原理与结构，并运用VHDL语言在FPGA芯片上模拟实现了绝大部分的传统误码仪的功能，，如LCD显示出来驱动driver，串口通信驱动driver，误码测试，数据存储芯片驱动driver等功能. -Study the working principle and structure of the traditional BERT, and the use of VHDL language to simulate most of the traditional BERT fu
data_scanC-
- PS/2键盘通信控制电路的数据扫描电路VHDL程序-PS2keyboard VHDL
fpga_uarst
- fpga USART通信，VHDL语言编写，通过测试。程序全面运用了状态机编程-The fpga the USARTs communications, VHDL language, pass the test. The entire process of the use of state machine programming
vhdl_can_IP.tar
- 运用VHDL语言实现的一个CAN通信控制器IP核-Communication of a CAN controller IP core using VHDL language
agc
- 无线通信中接收侧自动增益控制模块的vhdl代码实现-Receive side of the AGC module vhdl code for wireless communications
EX28_CPLD
- Quartus编程环境下，DSP5509与CPLD的通信过程，用VHDL来编写的。-The connection between DSP and CPLD