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FPGA
- 数字钟，实验程序描述，vhdl语言描述，看电视剧广发卡三季度发卡了-Digital clock, experimental procedures described, vhdl language descr iption, watching TV wide hairpin hairpin three quarters of the
clock
- 用VHDL编写的数字钟，可以走时，读秒，用作闹铃，整点报时-Using VHDL digital clock, you can take time, countdown, for alarm, hourly chime, etc.
alarm
- VHDL，多功能数字钟：具有年、月、日、时、分、秒计数显示功能，以24小时循环计数；具有整点报时功能；可以对年、月、日、时、分及秒进行单独校对，使其校正到标准时间-VHDL, multifunction digital clock: a year, month, day, hour, minute, seconds count display features a 24-hour cycle The whole point timekeeping function possible for
Digital-clock-design
- 数字钟设计 用VHDL实现一个50MHZ到1HZ的分频器，利用Quartus II进行文本编辑输入和仿真硬件测试。实现一个60进制和24进制的计数器。测试成功。-Digital clock design using VHDL a 50MHZ to 1HZ divider using Quartus II simulation for text input and editing hardware test. Achieve a 60 hex and 24 hex counter. Test wa
SHUZIZHONG
- VHDL语言编写的数字钟程序，在quartus软件下编写。-VHDL language digital clock program, prepared in quartus software.
gcounter1
- 数字钟vhdl实现，在线测试无误，具有闹钟，对表功能-Digital clock vhdl implementation, online testing is correct, with alarm, the table function
sy
- 利用VHDL语言设计的电子数字钟，有时、分钟、秒钟计数器、还有整点报时报警。-Design using VHDL language electronic digital clock, sometimes, minutes, seconds counter, as well as the whole point timekeeping alarm.
clockhms
- 自己写的数字钟源程序，VHDL语言，50M晶振，24小时计时制，可以清零，较时，闹钟。-I design a 24hr clock set, VHDL language, 50M crystals, it can be reset, relatively, the alarm clock
digtal_clock
- FPGA实现数字钟VHDL语言编写,包涵整点报时，清零，调时调分等功能-FPGA digital clock VHDL language, includes the whole point timekeeping, cleared when the transfer function of adjusting grading
shuzizhong
- vhdl数字钟通过fpeg仿真实现vhdl实验课设 -vhdl digital clock
component_timer_counter
- Quartus环境下基于VHDL元件例化的数字钟程序-Zhong Chengxu digital VHDL component instantiation based on Quartus environment
shuzizhong
- 数字钟，校时较分，显示,用元件例化写的vhdl文件，两个24进制，1个60进制计数器-Digital clock, when the school over the points, show cases with elements of writing vhdl file, two 24-band, a 60-ary counter
the-digital-clock
- 本设计选用 ALTERA 公司的 EP1C12Q240C8 芯片，利用 VHDL 语言采用自 顶向下的方法在 Quartus Ⅱ环境下完成了数字钟的设计，最后在实验箱上进行测 试。该数字钟包含的功能有计时、显示星期、校时校分、清零、整点报时、音乐 闹铃。-The design uses the silicon chip EP1C12Q240C8 produced by the company of ALTERA. And with the help of VHDL, the de
digitalclock
- 数字钟 初学VHDL时可参考 模10状态机 83译码器-Refer to die 10 when the state machine 83 decoder VHDL digital clock beginner
dig_clk
- 实现vhdl数字钟 实现时分秒调时 消抖等功能 采用quartus编程实现 -digital clock
digital-clock
- 用FPGA实现数字钟功能，用VHDL语言编写，含有课程设计报告-FPGA digital clock
shuzizhong
- 在ise平台上用VHDL语言实现数字钟，具有计时和重置时间功能、整点报时功能、闹钟功能，每个功能都使用元件例化的方法，通过顶层文件将每一个模块联系在一起。-On ise platform using VHDL digital clock with timer and reset the time function, the whole point timekeeping function, alarm clock function, each function using the compone
shuzizhong
- 基于VHDL语言的数字钟，有元件例化，修改时钟功能 Quartus II平台-VHDL language based digital clock, there are component instantiation, modify clock function Quartus II platform
Digital-clock
- 设计一个数字钟，使用vhdl语言进行编写，以上是源程序-The design of a digital clock, using VHDL language, the above is the source
EDA
- EDA实验程序：60进制，数字钟 ，表决器 包括VHDL语言和图的连线-EDA experimental procedure: 60 binary, digital clock, voting Including connection VHDL language and graphs