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frequency发生器
- vhdl语言实现的频率发生器，可以产生不同的频率-A frequency generator wirriten by VHDL, which can generate different frequecies.
一个波形发生器和sine波形发生器
- 这是一个典型的正玄波发生器程序和一个任意波形发生器程序，大家可以参考学习，对于vhdl入门还是很有帮助的-This is a typical wave generator Shogen procedures and an arbitrary waveform generator procedures, Members can take a learning portal for VHDL or helpful
加法
- 测试向量波形产生：VHDL实例---加法器源程序 -test vector Waveform Generator : VHDL example -- Adder source
8bitsine
- 8bit采样sine波形发生器,一共两个文件，各自用VHDL和VERILOG编写，通信开发平台专用-8bit sampling sine wave generator, a total of two papers, each with VHDL and VERILOG preparation, communications development platform dedicated
vhdl
- 用计数器、3/8译码器和门电路设计序列信号发生器用示波器观察并测量波形。-Counter, 3/8 decoder circuit design sequence and doors to observe and measure the waveform signal generator with an oscilloscope.
VHDL
- 正弦波发生器代码VHDL 其中包括分频 正弦波数据-Sine wave generator VHDL code Divide the sine wave data including
task-generator
- TASK GENERATOR VHDL CODE
VHDL
- 先设计序列发生器产生序列：1011010001101010；再设计序列检测器，检测序列发生器产生序列，若检测到信号与预置待测信号相同，则输出“1”，否则输出“0”，并且将检测到的信号的显示出来。-First design sequence generator sequence: 1011010001101010 redesign sequence detector to detect sequence generator sequence, if the same signal is dete
vhdl
- 伪随机序列发生器的vhdl算法 设计一个伪随机序列发生器，采用的生成多项式为1+X^3+X^7。要求具有一个RESET端和两个控制端来调整寄存器初值（程序中设定好四种非零初值可选）--Design of VHDL algorithm for pseudo random sequence generator is a pseudorandom sequence generator, using the generating polynomial 1+X^3+X^7. RESET has a cli
Pulse-Generator-Final-Zip
- A VHDL pulse generator that generates customizable square wave pulses on an arbitrary number of channels. Controlled by UART communication through serial port. Tuned for 5ns period clock signal. The pulse width and delay of each channel is fully
pseudo-random-number-VHDL
- 伪随机序列发生器的vhdl软件，有m序列和gold序列的算法-pseudo random number generator
Signal-Generator-VHDL-design
- 信号发生器VHDL设计 波形可选：正弦(sine)，方波(sqr)，锯齿波(jc_de和jc_in两种)，三角波(sanj)和阶梯波(stair)信号模块-Optional waveform signal generator VHDL design: sinusoidal (sine), square wave (sqr), sawtooth (jc_de and jc_in two kinds), triangle wave (sanj) and staircase (stair) sig
Controllable-pulse-generator-design
- 1、了解可控脉冲发生器的实现机理。 2、学会用示波器观察FPGA产生的信号。 3、学习用VHDL编写复杂功能的代码。 - Controllable pulse generator design
PWM
- VHDL code for PWM Generator with Variable Duty Cycle
BPSK
- BPSK信号的载波调制，包含成型滤波器，上采用器以及载波生成器。(This file provides a transmitter based on BPSK signal, including shaping filter, upsampler and carrier generator.)
kao_ad71
- EULER numerical analysis method, Verify recognition algorithm based on palmprint recognition undergraduate complete set of online identity, Gaussian white noise generator.
vhdl_rand
- Linear Feedback Shift Register (LFSR)/Random number generator
ZufallszahlengeneratorVHDL
- random number generator - 16bit
pwm_ok_PWM产生器
- 用于产生占空比任意可调的PWM产生器。PWM,即Pulse-Width Modulation 脉宽调制，常用于电机的控制中。(It is used to generate any adjustable PWM generator. PWM, namely Pulse-Width Modulation pulse width modulation, is commonly used in motor control.)
text seven
- VGA彩条信号显示器设计 设计并调试好一个VGA彩条信号发生器，并用EDA实验开发系统（拟采用的实验芯片的型号可选Altera CycloneII系列的 EP2C5T144C8 FPGA。(A VGA color bar signal generator is designed and debugged, and an EDA experimental development system is used (the model of the experimental chip to be use