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vhld_fpga_box
- Verilog 编写的波形发生器，可发生正弦波，三角波，方波，可以调频-Prepared Verilog waveform generator, can occur sine, triangle wave, square wave, you can FM
fpgada0832
- 该波形发生器以单片机(MCS8031)为中心控制单元，由键盘输入模块、数码管显示模块、D/A波形发生模块dac0832、幅值调整模块组成。采用DDFS技术，先将要求的波形数据存储于EEPROM中，这样可以保证掉电以后波形数据不丢失。-The waveform generator to single-chip microcomputer (MCS8031) as the central control unit, by the keyboard input module, digital tube
Multi_function_waveform_generator
- 多功能波形发生器VHDL程序与仿真.实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出（方波A的占空比也是可控的），可以存储任意波形特征数据并能重现该波形，还可完成各种波形的线形叠加输出。 -Multi-function waveform generator and simulation of VHDL procedures. The realization of four kinds of common sine wave, triangle, sawtooth, squ
VHDL
- 运用VHDL描述函数发生器的各个波形，可有构成多功能函数发生器。-VHDL descr iption of the use of various function generator waveforms, can constitute a multi-purpose function generator.
cordic
- 基于CORDIC算法的指数函数生成器的各种理论基础，通俗易懂-CORDIC algorithm based on exponential function generator for a variety of theoretical basis, user-friendly
dds9851
- 本文主要介绍的是采用直接数字频率合成的短波信号发生器，它主要以微电脑控制部分、直接数字频率合成（DDS）部分、数字锁相环频率合成部分、背光液晶显示部分、功率放大部分等组成。该软件系统采用菜单形式进行操作，操作方便明了，增加了很多功能。它通过启动DDS后，把内存缓存区的数据送到DDS后输出相应的频率，并把数据转换为BCD码，送到液晶显示器进行显示。该系统输出稳定度、精度极高，适用于当代的尖端的通信系统和精密的高精度仪器。-This paper describes the use of direct
FPGA_VHDL_sinusoidal_function
- 该文件包含基于VHDL的正弦信号发生器的设计源码-This file contains the VHDL-based design of sinusoidal signal generator source code
waveform
- 自己做的一个波形发生器，有兴趣的可以看下-Myself as a waveform generator may be interested in Kanxia
DDSFunctionGenerator
- 能实现频率步进100hz的信号发生器，频率可调。100-20khz.-To achieve step-100hz frequency signal generator, frequency adjustable. 100-20khz.
random
- 伪随机数产生器,可以根据输入的控制字产生需要的伪随机数-Pseudo-random number generator
URAT_VHDL
- URAT VHDL程序与仿真，包括顶层程序与仿真，波特率发生器VHDL程序， UART发送器程序与仿真，UART接收器程序与仿真-URAT VHDL procedures and simulation, including the top-level procedures and simulation, VHDL program baud rate generator, UART transmitter and simulation program, UART receiver and simu
fft_gen
- FFT vhdl generic: I m new to vhdl, and I tried to use xilinx fft core, but when I try to simulate it in test bench using ise simulator, I get zero results. here is what I do: 1- from core generator I choose fft core and create .vhd & .vho &
ddfs
- vhdl编的dds函数发生器，完成sin(x)曲线的生成-vhdl function generator dds compiled to complete the sin (x) curve is generated
vhdl
- 基于vhdl开发的频率发生器-Based on the development of frequency generator vhdl
func_gen
- This code that genetes a square, sawtooth and a triangular waveform. It is useful for designing a function generator in VHDL.
weisuiji
- 伪随机比特发生器， VHdL写的伪随机比特发生器-Pseudo-random bit generator, pseudo-random bit generator, VHdL written in pseudo-random bit generator,
dianziqin
- 这个程序是利用Quartus II编写的利用数控分频器设计硬件电子琴，主系统由3个模块组成，顶层设计文件内部有三个功能模块：SPEAKER.VHD 和TONE.VHD和NoteTabs.vhd。模块TONE是音阶发生器，模块SPEAKER中的主要电路是一个数控分频器，NOTETABS模块用于产生节拍控制和音阶选择信号。-This program is the use of Quartus II design prepared by the use of CNC divider hardware
sine_wave_generator_using_FPGA_implementation
- 该资料介绍了用FPGA实现正弦波发生器，原理是利用内置rom表，通过查询的方式实现输出，然后经过外部DAC输出，频率达到1MHz-The information on the sine wave generator using FPGA implementation, the principle is the use of built-in rom form, by querying the means to achieve the output, and then an external DA
SVPWMsignalgeneratoroftheVHDLimplementation
- SVPWM信号发生器的VHDL实现,收费硕士论文,文章详细研究了SVPWM波的VHDL实现方法.-SVPWM signal generator of the VHDL implementation, charging master paper, the article detailed study of the SVPWM wave VHDL implementations.
k_9_rate_1-2_VHDL
- viterbi generator its very good for convolution