搜索资源列表
CRC-Generator-for-Verilog-or-VHDL
- CRC Generator for Verilog or VHDL-CRC Generator for Verilog or VHDL
VHDL-based-design-of-SPI
- 基于VHDL的串行同步通信SPI设计 本设计是用Quartus作为开发环境，以DE2板为硬件平台实现的SPI同步串行通讯。设计过程方便。根据接收和发送两个主要部分实现了SPI的基本功能。此外，该设计还实现了波特率发生器，数码管显示的功能。用DE2板实现具有电路简洁，开发周期短的优点。充分利用了EDA设计的优点。开发过程用了VHDL硬件描述语言进行描述，从底层设计，分模块进行，充分提高了设计者的数字逻辑设计的概念。-VHDL-based SPI serial synchronous comm
Function-Generator
- 函数发生器，ＶＨＤＬ的综合实验 可以产生不同的函数，并将它输出。-Function generator, VHDL comprehensive experiment can have different functions, and output it.
convolution
- convolution卷积码生成器程序设计及仿真源代码-convolution convolutional code generator source code of program design and simulation
PCK_CRC3_D4
- CRC校验码生存程序 校验序列码生成多项式： X16+X13+X12+X11+X10+X8+X6+X5+X2+1 输入数据为16个字节（128位），输出16bit校验序列-CRC, the survival program check sequence code generator polynomial: X16+ X13+ X12+ X11+ X10+ X8+ X6+ X5+ X2+1 input data is 16 bytes (128 bits), output 16bit
VHDL
- VHDL程序(含任意波发生器，一些芯片的驱动，以及状态机的典型设计等)-VHDL program (including arbitrary waveform generator, a number of driver chips, and a typical state machine design, etc.)
vhdl
- 8421BCD码同步计数器,序列信号发生器,状态机设计-8421BCD code synchronization counter, serial signal generator, the state machine design
SG_FPGA
- 2006年电子设计竞赛二等奖，多功能函数、信号发生器核心器件FPGA内部的原理图，主要模块用VHDL代码描述，包括PLL、相位累加器、波形算法和正弦波查找表，可实现0.005Hz~20MHz的多波形信号产生，频率步进值0.005，输出接100MSPS速率的DAC--AD9762-Electronic Design Competition 2006, second prize, multi-function signal generator within the core of the devic
dds
- 基于vhdl的dds信号发生器，可产生方波，三角波，正弦波，幅度，频率，相位可调-The signal generator based on VHDL DDS, can produce square wave, triangle wave, sine wave, amplitude, frequency, phase can be adjusted
wave-generator(vhdL0
- 10章 波形信号发生器 vhdl波形发生器很有学习价值-Waveform signal generator VHDL is learning value waveform generator
songer
- 著名歌曲《十送红军》音乐发生器在FPGA上实现-The famous song " Shisonghongjun" music generator in the FPGA
Signal-Generator-VHDL
- 这是基于quartus dds信号发生器设计的源程序-This is based on quartus dds source signal generator design
Verilog-hdlFPGA
- 关于FPGA的提高篇，Verilog HDL语言写的， 包含LCD控制VHDL程序与仿真，AD/DA，MASK，FSK，PSK，正弦波发生器，等等经典程序-Articles on improving the FPGA, Verilog HDL language, and includes LCD control procedures and VHDL simulation, AD/DA, MASK, FSK, PSK, sine wave generator, and so the classi
FPGA-M-sequence-generator
- FPGA VHDL 语言M序列发生器，可以帮助各位需要的朋友探讨研究-FPGA VHDL language M-sequence generator, can you help a friend in need of research
DDS
- verilogHDL语言编写，带测试文件DDS波形发生器.-DDS waveform generator, verilogHDL language, with the test file
Baseband-code-generator-program
- 基带码发生器 功能：基于VHDL硬件描述语言，产生常用基带码-Baseband code generator program use IEEE.STD_LOGIC_1164.ALL use IEEE.STD_LOGIC_ARITH.ALL use IEEE.STD_LOGIC_UNSIGNED.ALL
vhdl-code-for-sine-wave-generator
- it is a simple code in vhdl for sine wave generator. the test bench code is also provided in ths code
VHDL-node
- VHDL的一些实验代码，其中有4位可逆计数器，4位可逆二进制代码－格雷码转换器设计、序列检测器的设计、基于ROM的正弦波发生器的设计、数字密码锁的设计与实现-Some experiments of VHDL code, which has four reversible counters, four reversible binary code- Gray code converter design, sequence detection Design, ROM-based sine wav
VHDL-design-example
- 用VHDL设计数字系统实例，VHDL写的一些实例，如波形发生器等-Using VHDL to design digital system examples, written in VHDL some examples, such as waveform generator
vhdl
- VHDL实验报告 基于ROM的正弦波发生器的设计-VHDL experiment reports the ROM-based sine wave generator design