搜索资源列表
grlib-gpl-1.0.15-b2149.tar
- free hardware ip core about sparcv8,a soc cpu in vhdl-free hardware ip core about sparcv8. a soc cpu in vhdl
SoC_WishboneSystem
- SoC-Wishbone System IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。
sdram_ctrl.tar
- 同步动态RAM的控制电路VHDL源代码,在SOC开发中可以直接应用
uart_serial
- UART接口的VHDL源代码，成功应用于SOC项目开发中，请勿用于商业用途。
SoCWishboneSystem
- SoC-Wishbone System IP核的VHDL语言源代码-SoC-Wishbone System IP core language VHDL source code
AVR_Core
- 用VHDL语言实现的AVR_Core,对于研究SOC很有帮助-Achieved using VHDL language AVR_Core, very helpful for studying SOC
aqz
- a：闲置不用GW48 EDA/SOC系统时，关闭电源，拔下电源插头！！！ b：EDA软件安装方法可参见光盘中相应目录中的中文README.TXT；详细使用方法可参阅本书或《EDA技术实用教程》、或《VHDL实用教程》中的相关章节。 c：在实验中，当选中某种模式后，要按一下右侧的复位键，以使系统进入该结构模式工作。 d：换目标芯片时要特别注意，不要插反或插错，也不要带电插拔，确信插对后才能开电源。其它接口都可带电插拔（当适配板上的10芯座处于左上角时，为正确位置）。 e
mesh_dft
- 自己写一个关于维mesh结构的noc网络，verilog，仿真结果无误。-Write their own structure on the noc-dimensional mesh network, verilog, accurate simulation results.
quick_reference
- SPECMAN LEARNING MATERIAL FOR VERIFICATION OF VHDL VERILOG SOC
Lantern---the-frequency-meter
- 可编程器件SOC的“彩灯-频率计”教学PPT，内含代码。 采用VHDL语言，感兴趣的同学可以看看。-Programmable devices SOC Lantern- frequency meter teaching PPT, containing the code. Using VHDL language, interested students can take a look.
vhdl-for-bluetooth
- bluetooth source code using soc and avr. the signal between soc and avr needs a basic rule in order to flow the signal
grlib-netlists-1.1.0.tar
- leon for 3 fpu. The LEON3 is a synthesisable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture. The model is highly configurable, and particularly suitable for system-on-a-chip (SOC) designs.
SOC-pracs----43
- VHDL CODE FOR system on Chip pracs pune University ME 2013 PATTERN
Extras_Edge_Detection
- ALTERA DE1 SOC VHDL SOURCE CODE
LTM_timing_controller
- vhdl file used for de2 soc to be completed