搜索资源列表
zhongzhilvbo
- xilinx ise 与modesim联合验证中值滤波 含verilog源程序和整个工程文件-the xilinx ise modesim median filter containing joint verification verilog source, and the entire project file
fpga_Uart
- 串口通信控制器 verilog实现含波特率发生模块，发送、接收模块程序以及xilinx所有工程文件-The serial communication controller verilog containing the baud rate generator module, send, receive module program xilinx all project files
fpga-fir
- xlinx fpga 利用verilog语言实现fir滤波器功能，完整ise工程文件直接可以使用-xlinx fpga verilog language the fir filter function, complete ise project file can be used directly
uart16550_latest.tar
- UART16550是较为通用的串口协议，压缩包内有4个文件可供选择，直接提供RTL源码，可直接导入到工程内。-Uart16550 core is used for Serial Commuication.There are 4 folders in the zip package and have the verilog RTL which can be added in the project.
fifo
- 异步fifo ,verilog 源代码，含工程文件，modosim 下运行-Asynchronous fifo verilog source code containing the project file run modosim
4.18
- verilog的测试工程，实现多种初学者必要的学习编写测试。非常好的菜鸟装备！-the verilog test engineering, beginners necessary to learn to write tests. Very rookie and equipment!
compare
- 三个数的比较，输出最大值，Verilog实现，已经建立modelsim工程，可以直接观看波形， Verilog 最大值，fpga-Verilog max value
KEYBOARD
- 用Verilog实现的按键检测及消抖程序代码，工程中很有实用价值。-Achieved using Verilog key detection and debounce code, works great practical value.
state_machine
- verilog编程状态机实战训练：1.本实例通过实现一个状态机来控制8个LED循环闪亮； 2. 工程在project文件夹里面； 3. 源文件和管脚分配在rtl文件夹里面； 4. 下载文件在download文件夹里面。-verilog programming state machine combat training: 1. This example by implementing a state machine to control 8 LED flashing cycle 2
ic2
- 一个IC2的verilog HDL设计，包含了modelsim的工程文件。-This is a IC2 design, which is simulated successfully in modelsim.
fir_filter_50Mhz
- 基于并行分布式算法的高速Fir滤波器的设计代码，采用Verilog编写，压缩包为quartus II编译过的工程代码-Parallel and distributed algorithms based on a high-speed Fir filter design code, Verilog prepared, compressed package for the quartus II compiled project code
fpga-jpeg
- 包含DCT变换，RGB2YCBCR,JPEG等多个verilog代码及工程-Contains DCT transform, RGB2YCBCR, JPEG and many other verilog code and project
zs
- 基于fpga的数字频率计，verilog编写，可修改闸门宽度0.1s/1s/10s，可测频率1hz~1mhz，包含整个工程，内部分频模块为了仿真方便改小了，后面注释为50mhz晶振下的分频值，可根据需要自行修改-Fpga-based digital frequency meter, verilog prepared to modify the gate width 0.1s/1s/10s, measurable frequency 1hz ~ 1mhz, contains the entire
chengfaleijia
- verilog 乘法累加器 包括工程项目及仿真波形图-verilog multiplier-accumulator including the project and the simulation waveform
pinlvji
- verilog 简易频率计的设置，包括整个工程-verilog simple frequency meter settings, including the entire project
FPGA_Verilog
- 这是《数字信号处理FPGA实现第三版》verilog代码，希望对你们的工程或者学习有帮助。上传只为了学习交流。-This is the " digital signal processing FPGA realization of the third edition of" verilog code, I hope your project or study help. Upload only for learning exchanges.
Watch_Game_0729
- 基于xilinx virtex5的猜数游戏+LCD显示设计，包含完整的ISE工程文件，代码全部用verilog编写，有说明文档。-Based on xilinx virtex5， the guessing game plus LCD display design, including complete ISE project file, all code written in verilog, documents.
CycloneII-VerilogV
- Altra CyloneII Verilog文件，共有18个工程，包括标准键盘、串口、VGA、EEPROM、LCD1602等操作源码-Altra CyloneII Verilog files,include keyboar.com.VGA、EEPROM、LCD1602 operation surce codes
1602test
- Verilog AD转换1602显示，用QuartusII编写的。完整的工程，好使！-Verilog AD converter 1602, with QuartusII prepared. Complete works, so that!
Cyclone4_SD_Card_Audio_Player
- 基于cyclone4 FPGA芯片的音频播放器完成项目工程，包括SOPC项目代码，以及SD卡读取模块Verilog IP，以及完整的Q2下项目工程。-Cyclone4 FPGA chip based audio player to complete the project works, including the SOPC project code, and SD card reader module IP, as well as complete Q2 next project.