搜索资源列表
Cyclone4_115_IR
- FPGA下红外收发项目工程，基于cyclone4 芯片，包括项目verilog源码已经sof下载文件，对于基于fpga的红外模块开发很有参考价值。-Project under infrared transceiver FPGA based cyclone4 chips, including project sof verilog source code has been downloaded files for fpga-based infrared module development of
iic_top
- iic协议的功能实现verilog HDL代码，并用7段数码管进行验证，压缩包内含有整个工程文件。-function iic protocol implementation verilog HDL code and seven-segment LED to verify, compressed package file containing the entire project.
netfpga_full_3_0_1.tar
- NetFPGA开发基础包，里面有相关的实例工程，也有相关的源码，verilog HDL，C，JAVA等-NetFPGA development base package, there are examples of related works, there are also relevant source, verilog HDL, C, JAVA, etc.
cordic_IP_EP1C
- verilog编写的调用cordicIP核实现sin信号的完整工程-call cordicIP sin signal to achieve complete nuclear engineering verilog prepared
paobiao
- ISE仿真平台下建立的用verilog语言实现的简易数字跑表工程-Simple digital stopwatch works with verilog language of the establishment of the ISE simulation platform
Digital_Clock1
- 基于Basys2多功能数字钟 verilog HDL 完整工程文件-Based Basys2 multifunction digital clock verilog HDL complete project file
iir_50hz
- IIR50Hz数字工频陷波，Altera cyclone2开发板，Quartus9.1软件工程的文件，Verilog HDL代码。-IIR50Hz digital frequency notch, Altera cyclone2 development board, Quartus9.1 project files, Verilog HDL code.
8-bit-RISC_CPU
- 8位RISC_CPU设计的verilog源码以及工程文件、测试数据文件。在modelsim 10.1d下验证成功，打开工程文件即可使用。-8 RISC_CPU design verilog source code and project files, test data files. In modelsim 10.1d validation is successful, open the project file can be used.
Float_add
- 该源码利用Verilog HDL语言成功实现了浮点数的加法运算，包括全部工程以及Verilog 源码，经验证，该程序成功实现了浮点数的加法。-The use of Verilog HDL source language of the successful implementation of floating-point addition operation, including all engineering and Verilog source code, proven, successful
eda
- 用verilog硬件描述语言编写的电子琴工程，实现手动弹奏21个音符，自动播放内置音乐，在显示器上模拟显示按键等功能。-Using verilog hardware descr iption language organ works, play 21 notes for manual, automatic built-in music player, analog display buttons on the monitor and other functions.
run_led
- Xilinx FPGA, ISE工程文件，Verilog语言实现流水灯，设计了分频器，可精确到点亮时间为一秒，可控制流水灯左右移位方向-Xilinx FPGA, ISE project file, Verilog language water lights, designed divider, accurate to one second light time, you can control the direction of light water left shift
ssram_latest.tar
- SSRAM接口,就是同步静态随机存取存储器接口整个工程文件，包括从前端verilog设计到后端仿真的整个工程-SSRAM interface is synchronous static random access memory interface entire project, including the design from the front to the back verilog simulation of the entire project
LEDhuadong
- LEDhuadong，是基于quarterii写的Verilog程序，可以下载到板子上，是一个工程文件-LEDhuadong, is based quarterii write Verilog program that can be downloaded to the board, is a project file
Digital_Logic_Design_FPGA
- 用verilog语言编写的程序，哈工大电子信息工程专业FPGA课程编写程序- Using verilog language program, HIT Electronic and Information Engineering FPGA programming courses
Lab5.5_Led_FPGA
- 使用verilog在fpga开发板实现流水灯，包括整个工程文件-This code is used for early learners to study verilog。
FSM
- 用verilog语言编写的状态机，包括状态机的各种标准写法，包括了modelsim的整个工程。-This code is used to describe the FSM. And it includes all modes of it.
SDRAM_96M_UART_TestOK
- SDRAM_96M_串口实验OK 一个项目工程，硬件包含Altera FPGA，SDRAM，串口，使用verilog-SDRAM_96M_ serial experiments OK a project engineering, hardware contains Altera FPGA, SDRAM, serial port, using verilog
DACtoADCtoSPI_Triangle1
- DACtoADCtoSPI_Triangle1.zip 一个项目工程，硬件包含Altera FPGA，SDRAM，串口，使用verilog-DACtoADCtoSPI_Triangle1.zip a project engineering, hardware contains Altera FPGA, SDRAM, serial port, using verilog
cic_cq
- 在altera平台用verilog硬件描述语言实现cic抽取滤波，包含完整的工程代码，已经仿真通过，可以直接用于实践-In the Altera platform using Verilog hardware descr iption language CIC decimation filter, contains the complete project code, has been adopted by simulation, can be used directly in practice
cic_cz
- 在altera平台用verilog硬件描述语言实现cic插值滤波，在modelsim软件中仿真通过，包含完整的工程代码，可以直接下载到FPGA中运行-In the Altera platform using Verilog hardware descr iption language CIC interpolation filter, through the simulation in Modelsim software, including the complete project co